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| 型號： | EVAL-ADAU1401EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADAU1401 |
| 標準包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻編解碼器 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1401 |
| 主要屬性： | 在 50-MIPS 時的 28/56 位音頻處理器，2 ADC，4 DAC |
| 次要屬性： | 均衡，交叉，低音增強，多頻帶動態(tài)處理，延遲等 |
| 已供物品： | 2 個板，線纜，電源 |
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ADAU1401
Data Sheet
Rev. C | Page 30 of 52
SIGNAL PROCESSING
The ADAU1401 is designed to provide all audio signal processing
functions commonly used in stereo or multichannel playback
systems. The signal processing flow is designed using the
SigmaStudio software, which allows graphical entry and real-
time control of all signal processing functions.
Many of the signal processing functions are coded using full,
56-bit, double-precision arithmetic data. The input and output
word lengths of the DSP core are 24 bits. Four extra headroom
bits are used in the processor to allow internal gains of up to
24 dB without clipping. Additional gains can be achieved by
initially scaling down the input signal in the DSP signal flow.
NUMERIC FORMATS
DSP systems commonly use a standard numeric format.
Fractional number systems are specified by an A.B format,
where A is the number of bits to the left of the decimal point
and B is the number of bits to the right of the decimal point.
The ADAU1401 uses the same numeric format for both the
parameter and data values. The format is as follows.
Numerical Format: 5.23
Linear range: 16.0 to (+16.0 1 LSB)
Examples:
1000 0000 0000 0000 0000 0000 0000 = 16.0
1110 0000 0000 0000 0000 0000 0000 = 4.0
1111 1000 0000 0000 0000 0000 0000 = 1.0
1111 1110 0000 0000 0000 0000 0000 = 0.25
1111 1111 0011 0011 0011 0011 0011 = 0.1
1111 1111 1111 1111 1111 1111 1111 = (1 LSB below 0.0)
0000 0000 0000 0000 0000 0000 0000 = 0.0
0000 0000 1100 1100 1100 1100 1101 = 0.1
0000 0010 0000 0000 0000 0000 0000 = 0.25
0000 1000 0000 0000 0000 0000 0000 = 1.0
0010 0000 0000 0000 0000 0000 0000 = 4.0
0111 1111 1111 1111 1111 1111 1111 = (16.0 1 LSB).
The serial port accepts up to 24 bits on the input and is sign-
extended to the full 28 bits of the DSP core. This allows internal
gains of up to 24 dB without internal clipping.
A digital clipper circuit is used between the output of the DSP
core and the DACs or serial port outputs (see Figure 29). This
clips the top four bits of the signal to produce a 24-bit output
with a range of 1.0 (minus 1 LSB) to 1.0. Figure 29 shows the
maximum signal levels at each point in the data flow in both
binary and decibel levels.
4-BIT SIGN EXTENSION
DATA IN
1.23
(0dB)
1.23
(0dB)
1.23
(0dB)
5.23
(24dB)
5.23
(24dB)
SERIAL
PORT
SIGNAL
PROCESSING
(5.23 FORMAT)
DIGITAL
CLIPPER
0
675
2-
028
Figure 29. Numeric Precision and Clipping Structure
PROGRAMMING
On power-up, the ADAU1401 default program passes the
unprocessed input signals to the outputs (shown in Figure 13),
but the outputs are muted by default (see the Power-Up Sequence
section). There are 1024 instruction cycles per audio sample,
resulting in about 50 MIPS available. The SigmaDSP runs in a
stream-oriented manner, meaning that all 1024 instructions are
executed each sample period. The ADAU1401 can also be set up to
accept double- or quad-speed inputs by reducing the number of
instructions per sample that are set in the core control register.
The part can be easily programmed using SigmaStudio (Figure 30),
a graphical tool provided by Analog Devices. No knowledge of
writing line-level DSP code is required. More information about
SigmaStudio can be found at www.analog.com.
06
75
2-
0
29
Figure 30. SigmaStudio Screen Shot
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