參數(shù)資料
型號： EDX5116ADSE-3A-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits XDR⑩ DRAM
中文描述： 32M X 16 RAMBUS, PBGA104
封裝： ROHS COMPLIANT, FBGA-104
文件頁數(shù)： 68/78頁
文件大?。?/td> 3311K
代理商： EDX5116ADSE-3A-E
Data Sheet E1033E30 (Ver. 3.0)
68
EDX5116ADSE
DRSL DQ Transmit Timing
Figure 51 shows a timing diagram for transmitting read data on
the DQ15..0/DQN15..0 data pins of the memory component.
This diagram represents a magnified view of these pins and
only a few clock cycles are shown (CFM and CFMN are the
clock signals). Timing events are measured to and from the pri-
mary CFM/CFMN crossing point in which CFM makes its
high-voltage-to-low-voltage transition. The DQ15..0/
DQN15..0 signals are high-true: a low voltage represents a log-
ical zero and a high voltage represents a logical one. They are
also differential — timing events on the DQ15..0/DQN15..0
pins are measured to and from the point that each differential
pair crosses.
Because timing intervals are measured in this fashion, it is nec-
essary to constrain the slew rate of the signals. The rise
(t
OR,DQ
) and fall time (t
OF,DQ
) of the signals are measured
from the 20% and 80% points of the full-swing levels.
20% = V
OL,DQ
+ 0.2*(V
OH,DQ
-V
OL,DQ
)
80% = V
OL,DQ
+ 0.8*(V
OH,DQ
-V
OL,DQ
)
There are 16 data transmitting windows defined for each
DQ15..0/DQN15..0 pin pair. The transmitting windows for a
particular DQi/DQNi pin pair are referenced to an offset
parameter t
QOFF,DQi
(the index “i” may take on the values {0,
1, ..15} and refers to each of the DQ15..0/DQN15..0 pin
pairs).
The t
QOFF,DQi
parameter determines the time between the pri-
mary CFM/CFMN crossing point and the offset point for the
DQi/DQNi pin pair.
The offset values t
QOFF,DQi
for each of the 16 DQi/DQNi pin
pairs can be different. However, each is constrained to lie
inside the range {t
QOFF,MIN ,
t
QOFF,MAX
}. Furthermore, each
offset value t
QOFF,DQi
is static; its value will not change during
system operation. Its value can be determined at initialization
time.
The 16 transmitting windows (j=0..15) for the first pair DQ0/
DQN0 are labeled “0” through “15”. Each window begins at
the time (t
QOFF,DQ0
+t
Q,DQ,MAX
+((j - 0.5)/8)*t
CYCLE
) and
ends at the time (t
QOFF,DQ0
+t
Q,DQ,MIN
+((j+0.5)/8)*t
CYCLE
)
measured after the primary CFM/CFMN crossing point.
The 16 transmitting windows (j=0..15) for the other pairs
DQi/DQNi are also labeled “0” through “15”. Each window
begins at the time (t
QOFF,DQi
+t
Q,DQ,MAX
+((j - 0.5)/8)*t
CY-
CLE
) and ends at the time (t
QOFF,DQi
+t
Q,DQ,MIN
+((j+0.5)/
8)*t
CYCLE
) measured after the primary CFM/CFMN crossing
point.
Note that when no read data is to be transmitted on the DQ/
DQN pins (and no other component is transmitting on the
external DQ/DQN wires), then the voltage level on the DQ/
DQN pins will follow the voltage reference value
VTERM,DRSL on the VTERM pin. The logical value of each
DQ/DQN pin pair in this no-drive state will be “1/1”; when
read data is driven, each DQ/DQN pin pair will have either
the logical value of “1/0” or “0/1”.
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