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參數(shù)資料
| 型號： | EDX5116ADSE-3A-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits XDR⑩ DRAM |
| 中文描述： | 32M X 16 RAMBUS, PBGA104 |
| 封裝： | ROHS COMPLIANT, FBGA-104 |
| 文件頁數(shù)： | 3/78頁 |
| 文件大?。?/td> | 3311K |
| 代理商： | EDX5116ADSE-3A-E |
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Data Sheet E1033E30 (Ver. 3.0)
3
EDX5116ADSE
General Description
The timing diagrams in Figure 1 illustrate XDR DRAM device
write and read transactions. There are three sets of pins used
for normal memory access transactions: CFM/CFMN clock
pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins.
The “N” appended to a signal name denotes the complemen-
tary signal of a differential pair.
A
transaction
is a collection of packets needed to complete a
memory access. A
packet
is a set of bit windows on the signals
of a bus. There are two buses that carry packets: the RQ bus
and DQ bus. Each packet on the RQ bus uses a set of 2 bit-
windows on each signal, while the DQ bus uses a set of 16 bit-
windows on each signal.
In the write transaction shown in Figure 1, a request packet (on
the RQ bus) at clock edge T
0
contains an activate (ACT) com-
mand. This causes row Ra of bank Ba in the memory compo-
nent to be loaded into the sense amp array for the bank. A
second request packet at clock edge T
1
contains a write (WR)
command. This causes the data packet D(a1) at edge T
4
to be
written to column Ca1 of the sense amp array for bank Ba. A
third request packet at clock edge T
3
contains another write
(WR) command. This causes the data packet D(a2) at edge T
6
to be also written to column Ca2. A final request packet at
clock edge T
14
contains a precharge (PRE) command.
The spacings between the request packets are constrained by
the following timing parameters in the diagram: t
RCD -W
, t
CC
,
and t
WRP
. In addition, the spacing between the request packets
and data packets are constrained by the t
CWD
parameter. The
spacing of the CFM/CFMN clock edges is constrained by
t
CYCLE
.
Figure 1
X DR DRAM Devic e Write and Read Transac tions
The read transaction shows a request packet at clock edge T
0
containing an ACT command. This causes row Ra of bank Ba
of the memory component to load into the sense amp array for
the bank. A second request packet at clock edge T
5
contains a
read (RD) command. This causes the data packet Q(a1) at edge
T
11
to be read from column Ca1 of the sense amp array for
bank Ba. A third request packet at clock edge T
7
contains
another RD command. This causes the data packet Q(a2) at
edge T
13
to also be read from column Ca2. A final request
packet at clock edge T
10
contains a PRE command. The spac-
ings between the request packets are constrained by the follow-
ing timing parameters in the diagram: t
RCD -R
, t
CC
, and t
RDP
.
In addition, the spacing between the request and data packets
are constrained by the t
CAC
parameter.
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
Transaction a
: WR
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
t
CC
t
CWD
t
CYCLE
t
WRP
t
RCD-W
a1
WR
a2
WR
a3
PRE
a0
ACT
D(a2)
D(a1)
Write Transaction
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
Transaction a:
RD
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
t
CC
t
CAC
t
CYCLE
t
RDP
t
RCD-R
a1
RD
a2
RD
PRE
a0
ACT
Q(a2)
Q(a1)
Read Transaction
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDX5116ADSE-3B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR⑩ DRAM |
| EDX5116ADSE-3C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ADSE-4D-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR⑩ DRAM |
| EDXSPECTRUMDAT/5962R8773901VDA | 制造商:Analog Devices 功能描述:SPECTRUM ANALYSIS - Literature |
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