參數(shù)資料
型號(hào)： EDX5116ADSE-3A-E
廠商： ELPIDA MEMORY INC
元件分類(lèi)： DRAM
英文描述： 512M bits XDR⑩ DRAM
中文描述： 32M X 16 RAMBUS, PBGA104
封裝： ROHS COMPLIANT, FBGA-104
文件頁(yè)數(shù)： 65/78頁(yè)
文件大?。?/td> 3311K
代理商： EDX5116ADSE-3A-E
Data Sheet E1033E30 (Ver. 3.0)
65
EDX5116ADSE
RSL RQ Receive Timing
Figure 49 shows a timing diagram for the RQ11..0 request pins
of the memory component. This diagram represents a magni-
fied view of the pins and only a few clock cycles (CFM and
CFMN are the clock signals). Timing events are measured to
and from the primary CFM/CFMN crossing point in which
CFM makes its high-voltage-to-low-voltage transition. The
RQ11..0 signals are low-true: a high voltage represents a logical
zero and a low voltage represents a logical one. Timing events
on the RQ11..0 pins are measured to and from the point that
the signal reaches the level of the reference voltage V
REF,RSL
.
Because timing intervals are measured in this fashion, it is nec-
essary to constrain the slew rate of the signals. The rise (t
R,RQ
)
and fall time (t
F,RQ
) of the signals are measured from the 20%
and 80% points of the full-swing levels.
20% = V
IL,RQ
+ 0.2*(V
IH,RQ
-V
IL,RQ
)
80% = V
IL,RQ
+ 0.8*(V
IH,RQ
-V
IL,RQ
)
There are two data receiving windows defined for each
RQ11..0 signal. The first of these (labeled “0”) has a set time,
t
S,RQ
, and a hold time, t
H,RQ
, measured around the primary
CFM/CFMN crossing point. The second (labeled “1”) has a
set time (t
S,RQ
) and a hold time (t
H,RQ
) measured around a
point 0.5*t
CYCLE
after the primary CFM/CFMN crossing
point.
Figure 49
RS L RQ Rec eive Waveforms
t
S,RQ
CFM
CFMN
RQ0
t
H,RQ
t
CYCLE
RQ11
.
80%
20%
V
IL,RQ
logic1
t
R,RQ
V
IH,RQ
logic 0
V
REF,RSL
[1/2]t
CYCLE
0
1
t
S,RQ
t
H,RQ
t
F,RQ
t
S,RQ
t
H,RQ
80%
20%
V
IL,RQ
logic 1
t
R,RQ
V
IH,RQ
logic 0
V
REF,RSL
[1/2]t
CYCLE
0
1
t
S,RQ
t
H,RQ
t
F,RQ
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