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參數(shù)資料
| 型號(hào)： | EDE5108AJBG-8E-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits DDR2 SDRAM |
| 中文描述： | 64M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| 封裝： | ROHS COMPLIANT, FBGA-60 |
| 文件頁(yè)數(shù)： | 8/77頁(yè) |
| 文件大?。?/td> | 589K |
| 代理商： | EDE5108AJBG-8E-E |
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EDE5108AJBG, EDE5116AJBG
Preliminary Data Sheet E1044E20 (Ver. 2.0)
8
DC Characteristics 1 (TC = 0
°
C to +85
°
C, VDD, VDDQ = 1.8V
±
0.1V)
×
8
×
16
Parameter
Symbol
Grade
max.
max.
Unit
Test condition
Operating current
(ACT-PRE)
IDD0
-8E
-6E
55
50
70
65
mA
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
Operating current
(ACT-READ-PRE)
IDD1
-8E
-6E
65
60
85
80
mA
Precharge power-
down standby
current
IDD2P
-8E
-6E
10
10
10
10
mA
all banks idle; tCK = tCK (IDD); CKE is L;
Other control and address bus inputs are
STABLE;
Data bus inputs are FLOATING
Precharge quiet
standby current
IDD2Q
-8E
-6E
15
15
15
15
mA
all banks idle; tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are
STABLE;
Data bus inputs are FLOATING
all banks idle; tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
Idle standby current IDD2N
-8E
-6E
20
20
20
20
mA
IDD3P-F
-8E
-6E
15
15
15
15
mA
Fast PDN Exit
MRS(12) = 0
Active power-down
standby current
IDD3P-S
-8E
-6E
12
12
12
12
mA
all banks open;
tCK = tCK (IDD);
CKE is L;
Other control and
address bus inputs
are STABLE;
Data bus inputs
are FLOATING
Slow PDN Exit
MRS(12) = 1
Active standby
current
IDD3N
-8E
-6E
40
35
40
35
mA
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads,
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD),
tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD),
tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Operating current
(Burst read
operating)
IDD4R
-8E
-6E
125
110
170
145
mA
Operating current
(Burst write
operating)
IDD4W
-8E
-6E
120
105
160
140
mA
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相關(guān)代理商/技術(shù)參數(shù) |
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| EDE5108AJSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
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