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| 型號(hào)： | DV164136 |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 55/107頁 |
| 文件大?。?/td> | 0K |
| 描述： | DEVELOPMENT KIT FOR PIC18 |
| 產(chǎn)品培訓(xùn)模塊： | PIC18 J Series MCU Overview |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PIC® |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | PIC18F8722，PIC18F87J11 |
| 所含物品： | 板，線纜，CD，PICkit? 3 個(gè)編程器，電源 |
| 產(chǎn)品目錄頁面： | 659 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | PIC18F87J11-I/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP PIC18F87J11T-I/PTTR-ND - IC PIC MCU FLASH 64KX16 80TQFP PIC18F8722T-E/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP PIC18F8722-E/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP PIC18F8722T-I/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP PIC18F8722-I/PT-ND - IC PIC MCU FLASH 64KX16 80TQFP |
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2007-2012 Microchip Technology Inc.
DS39778E-page 51
PIC18F87J11 FAMILY
4.3
Sleep Mode
The power-managed Sleep mode is identical to the leg-
acy Sleep mode offered in all other PIC devices. It is
entered by clearing the IDLEN bit (the default state on
device Reset) and executing the SLEEP instruction.
This shuts down the selected oscillator (Figure 4-5). All
clock source status bits are cleared.
Entering Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see Figure 4-6), or it will be clocked
from the internal oscillator if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor are enabled
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCSx
bits are not affected by the wake-up.
4.4
Idle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS<1:0> bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(Parameter 38, Table 28-13) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCSx bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode,
currently specified by the SCS<1:0> bits.
FIGURE 4-5:
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
FIGURE 4-6:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q4
Q3
Q2
OSC1
Peripheral
Sleep
Program
Q1
Counter
Clock
CPU
Clock
PC + 2
PC
Q3 Q4 Q1 Q2
OSC1
Peripheral
Program
PC
PLL Clock
Q3 Q4
Output
CPU Clock
Q1
Q2 Q3 Q4 Q1 Q2
Clock
Counter
PC + 6
PC + 4
Q1 Q2 Q3 Q4
Wake Event
Note 1:
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
TOST(1)
TPLL(1)
OSTS Bit Set
PC + 2
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