I2
參數(shù)資料
型號： DSPB56364AF100
廠商： Freescale Semiconductor
文件頁數(shù)： 24/148頁
文件大?。?/td> 0K
描述： IC DSP 24BIT AUD 100MHZ 100-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： DSP56K/Symphony
類型： 音頻處理器
接口： 主機(jī)接口，I²C，SAI，SPI
時鐘速率： 100MHz
非易失內(nèi)存： ROM（24 kB）
芯片上RAM： 11.25kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
Serial Host Interface
DSP56364 Technical Data, Rev. 4.1
2-8
Freescale Semiconductor
HA0
Input
Tri-stated
I2C Slave Address 0—This signal uses a Schmitt-trigger input when configured for the
I2C mode. When configured for I2C slave mode, the HA0 signal is used to form the
slave device address. HA0 is ignored when configured for the I2C master mode.
This signal is tri-stated during hardware, software, and individual reset. Thus, there is
no need for an external pull-up in this state.
This input is 5 V tolerant.
SS
Input
SPI Slave Select—This signal is an active low Schmitt-trigger input when configured
for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable
the SPI slave for transfer. When configured for the SPI master mode, this signal should
be kept deasserted (pulled high). If it is asserted while configured as SPI master, a bus
error condition is flagged. If SS is deasserted, the SHI ignores SCK clocks and keeps
the MISO output signal in the high-impedance state.
HA2
Input
I2C Slave Address 2—This signal uses a Schmitt-trigger input when configured for the
I2C mode. When configured for the I2C Slave mode, the HA2 signal is used to form the
slave device address. HA2 is ignored in the I2C master mode.
This signal is tri-stated during hardware, software, and individual reset. Thus, there is
no need for an external pull-up in this state.
This input is 5 V tolerant.
HREQ
Input or
Output
Tri-stated
Host Request—This signal is an active low Schmitt-trigger input when configured for
the master mode but an active low output when configured for the slave mode.
When configured for the slave mode, HREQ is asserted to indicate that the SHI is ready
for the next data word transfer and deasserted at the first clock pulse of the new data
word transfer. When configured for the master mode, HREQ is an input. When asserted
by the external slave device, it will trigger the start of the data word transfer by the
master. After finishing the data word transfer, the master will await the next assertion of
HREQ to proceed to the next transfer.
This signal is tri-stated during hardware, software, personal reset, or when the
HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in
this state.
This input is 5 V tolerant.
Table 2-9 Serial Host Interface Signals (continued)
Signal
Name
Signal
Type
State During
Reset
Signal Description
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