- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1917 > DSPB56364AF100 (Freescale Semiconductor)IC DSP 24BIT AUD 100MHZ 100-LQFP PDF資料下載
參數(shù)資料
| 型號： | DSPB56364AF100 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 138/148頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT AUD 100MHZ 100-LQFP |
| 標(biāo)準包裝： | 90 |
| 系列： | DSP56K/Symphony |
| 類型： | 音頻處理器 |
| 接口： | 主機接口，I²C，SAI，SPI |
| 時鐘速率： | 100MHz |
| 非易失內(nèi)存： | ROM（24 kB） |
| 芯片上RAM： | 11.25kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁當(dāng)前第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁
External Memory Expansion Port (Port A)
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor
2-5
2.5.2
External Data Bus
2.5.3
External Bus Control
Table 2-6 External Data Bus Signals
Signal
Name
Type
State During
Reset
Signal Description
D0–D7
Input/
Output
Tri-stated
Data Bus—D0–D7 are active-high, bidirectional input/outputs that provide the
bidirectional data bus for external program and data memory accesses. D0–D7 are
tri-stated during hardware reset and when the DSP is in the stop or wait low-power
standby mode.
Table 2-7 External Bus Control Signals
Signal Name
Type
State During
Reset
Signal Description
AA0–AA1/
RAS0–RAS1
Output
Tri-stated
Address Attribute or Row Address Strobe—When defined as AA, these signals
can be used as chip selects or additional address lines. When defined as
RAS,
these signals can be used as
RAS for DRAM interface. These signals are
tri-stateable outputs with programmable polarity. These signals are tri-stated during
hardware reset and when the DSP is in the stop or wait low-power standby mode.
CAS
Output
Tri-stated
Column Address Strobe—
CAS is an active-low output used by DRAM to strobe
the column address. This signal is tri-stated during hardware reset and when the
DSP is in the stop or wait low-power standby mode.
RD
Output
Tri-stated
Read Enable—
RD is an active-low output that is asserted to read external memory
on the data bus. This signal is tri-stated during hardware reset and when the DSP
is in the stop or wait low-power standby mode.
WR
Output
Tri-stated
Write Enable—
WR is an active-low output that is asserted to write external
memory on the data bus. This signal is tri-stated during hardware reset and when
the DSP is in the stop or wait low-power standby mode.
TA
Input
Ignored Input
Transfer Acknowledge—If there is no external bus activity, the
TA input is ignored.
The
TA input is a data transfer acknowledge (DTACK) function that can extend an
external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be
added to the wait states inserted by the BCR by keeping
TA deasserted. In typical
operation,
TA is deasserted at the start of a bus cycle, is asserted to enable
completion of the bus cycle, and is deasserted before the next bus cycle. The
current bus cycle completes one clock period after
TA is asserted synchronous to
the internal system clock. The number of wait states is determined by the
TA input
or by the bus control register (BCR), whichever is longer. The BCR can be used to
set the minimum number of wait states in external bus cycles.
In order to use the TA functionality, the BCR must be programmed to at least one
wait state. A zero wait state access cannot be extended by TA deassertion,
otherwise improper operation may result.
TA can operate synchronously or
asynchronously, depending on the setting of the TAS bit in the operating mode
register (OMR).
TA functionality may not be used while performing DRAM type accesses, otherwise
improper operation may result.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSPB56366AG120 | IC DSP 24BIT AUD 120MHZ 144-LQFP |
| DSPB56367AG150 | IC DSP 24BIT 150MHZ 144-LQFP |
| DSPB56371AF180 | IC DSP 24BIT 180MHZ 80-LQFP |
| DSPB56374AEC | IC DSP 24BIT 150MHZ 52-LQFP |
| DSPB56720CAG | DSP 24BIT AUD 200MHZ 144-LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSPB56364FU100 | 制造商:Rochester Electronics LLC 功能描述:24 BIT AUDIO DSP - Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| DSPB56364FU100R2 | 制造商:Freescale Semiconductor 功能描述:DSP FIX PT 24BIT 100MHZ 100MIPS 100LQFP - Tape and Reel |
| DSPB56366AG120 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC LEAD FREE DSPB56366 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSPB56366PV120 | 制造商:Motorola Inc 功能描述: 制造商:Freescale Semiconductor 功能描述:IC 制造商:MOTOROLA 功能描述: |
| DSPB56367AG150 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 150Mhz/150MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。