參數(shù)資料
型號(hào)： DSD1702E
英文描述： ENHANCED MULTIFORMAT, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER
中文描述： 增強(qiáng)的多格式，Δ-Σ，音頻數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù)： 8/28頁(yè)
文件大?。?/td> 417K
代理商： DSD1702E
DSD1702
SLES005A
–
JUNE 2001
–
REVISED FEBRUARY 2002
8
www.ti.com
system clock and reset functions (continued)
Reset
Reset Remove
1024 System Clocks
2.4 V
2 V
1.6 V
VDD
Internal Reset
System Clock
Figure 2. Power-On Reset Timing
audio serial interface
The DSD1702 has two audio serial interface ports: PCM audio interface port and DSD audio interface port.
In PCM mode, the audio interface is a 3-wire serial port. It includes PLRCK (pin 5), PBCK (pin 3), and PDATA
(pin 4). PBCK is the serial audio bit clock, and it is used to clock the serial data present on PDATA into the serial
shift register of the audio interface. Serial data is clocked into the DSD1702 on the rising edge of PBCK. PLRCK
is the serial audio left/right word clock. It is used to latch serial data into the internal registers of the serial audio
interface.
DSD1702 requires the synchronization of PLRCK and system clock, but does not need a specific phase relation
between PLRCK and system clock.
If the relationship between PLRCK and system clock changes more than
±
6 PBCK, internal operation is
initialized within 1/f
s
and analog outputs are forced into 0.5 V
CC
until re-synchronization between PLRCK and
system clock is completed
.
In DSD mode, the audio interface port is also a 3-wire serial connection. DBCK (pin 20) is the serial audio bit
clock, and it is used to clock the individual direct stream digital (= DSD) audio data on DSDL (pin 1) and DSDR
(pin 2). DSD data is clocked into the DSD1702 on the rising edge of DBCK. DBCK must be synchronous with
the system clock, but does not require a specific phase relation to it. DBCK is operated at the DSD sampling
frequency, nominally 64
×
44.1kHz.
audio data formats and timing
In PCM mode, the DSD1702 supports industry-standard audio data formats, including standard, I
2
S, and
left-justified. The data formats are shown in Figures 3 and 4. Data formats are selected using the format bits,
FMT[2:0], in control register 20. The default data format is 24-bit standard format. All formats require binary 2s
complement, MSB-first audio data. Figure 5 shows a detailed timing diagram for the serial audio interface.
In DSD mode, the DSD1702 supports a DSD audio data format. The data formats are shown in FIGURE 5. The
data formats are selected automatically when DSD bit in control register 22 is set. Figure 6 shows a detailed
timing diagram for the DSD audio data interface.
serial control interface
The serial control interface is a 3-wire serial port which operates completely asynchronously to the serial audio
interface. The serial control interface is utilized to program the on-chip mode registers. The control interface
includes MD (pin 15), MC (pin 16), and MS (pin 17). MD is the serial data input, used to program the mode
registers. MC is the serial bit clock, used to shift data into the control port. MS is the chip select for control port.
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