參數(shù)資料
型號： DSD1702E
英文描述： ENHANCED MULTIFORMAT, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER
中文描述： 增強(qiáng)的多格式，Δ-Σ，音頻數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù)： 7/28頁
文件大?。?/td> 417K
代理商： DSD1702E
DSD1702
SLES005A
–
JUNE 2001
–
REVISED FEBRUARY 2002
7
www.ti.com
system clock and reset functions
system clock input
The DSD1702 requires a system clock for operating the digital interpolation filter, digital DSD filter and multilevel
delta-sigma modulator. The system clock is applied to PSCK (pin 18) in PCM mode and to DSCK (pin 19) in
DSD mode. When CKCE (control register 20, B7) is not set to 1, the system clock is also applied to PSCK in
DSD mode. The DSD1702 has a system clock detection circuit. Table I shows examples of system clock
frequencies for common audio sampling rates.
Figure 1 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise. Burr-Brown
’
s PLL1700 multiclock generator is an excellent
choice for providing the DSD1702 system clock.
In PCM mode, the over sampling rate of digital filter is 4 times when a 128f
S
and 192f
s
system clock is applied
to DSD1702. When a 256f
s
, 384f
s
, 512f
s
and 768f
s
is applied, the over sampling rate is eight times.
power-on reset functions
The DSD1702 includes a power-on reset function. Figure 1 shows the operation of this function. With
V
DD
> 2 V, the power-on reset function will be enabled. The initialization sequence requires 1024 system clocks
from the time V
DD
> 2 V as shown in Figure 2. After the initialization period, the DSD1702 will be set to its reset
default state, as described in the mode control register section of this data sheet.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
MODE
SAMPLING
FREQUENCY
SYSTEM CLOCK FREQUENCY (fSCLK) (MHZ)
192fs
256fs
3.072
4.096
128fs
2.048
384fs
6.144
512fs
8.192
768fs
12.288
16kHz
32kHz
4.096
6.144
8.192
12.288
16.384
24.576
44.1kHz
5.6488
8.4672
11.2896
16.9344
22.5792
33.8688
PCM
48kHz
6.144
9.216
12.288
18.432
24.576
36.864
88.2kHz
11.2896
16.9344
22.5792
33.8688
45.1584
67.7376
96kHz
12.288
16.84
24.576
36.864
49.152
73.728
192kHz
24.576
36.864
See Note 9
See Note 9
See Note 9
See Note 9
DSD
64x44.1kHz
—
—
11.2896
16.9344
22.5792
33.8688
NOTE 9: This system clock is not supported for the given sampling frequency.
L
H
0.8 V
2 V
System Clock Pulse
Cycle Time
tSCKH
tSCKL
System Clock
System Clock Pulse Width High
System Clock Pulse Width Low
tSCKH
tSCKL
5 ns (min)
5 ns (min)
Figure 1. System Clock Input Timing
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DSD1702E/2K 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 2 CH Enh Mlt-Format D-S DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
DSD1702E/2KG4 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 2 CH Enh Mlt-Format D-S DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
DSD1702EG4 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 2CH Enh Multi-Format Delta-Sigma Aud RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
DSD1751DBQ 制造商:Texas Instruments 功能描述:
DSD1791 制造商:TI 制造商全稱:Texas Instruments 功能描述:24 BIT 192 KHZ SAMPLING ADVANCED SEGMENT AUDIO STEREO DIGITAL TO ANALOG CONVERTER
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