參數(shù)資料
型號: DSD1702E
英文描述: ENHANCED MULTIFORMAT, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER
中文描述: 增強的多格式,Δ-Σ,音頻數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù): 20/28頁
文件大?。?/td> 417K
代理商: DSD1702E
DSD1702
SLES005A
JUNE 2001
REVISED FEBRUARY 2002
20
www.ti.com
zero flags and zero detect mute functions
The DSD1702 includes circuitry for detecting an all 0 data condition for the PCM audio data input pin. This
includes two independent functions: zero output flags and zero detect mute. Although the flag and mute
functions are independent of one another, the zero detection mechanism is common to both functions.
zero detect condition
Zero detection for each output channel is independent from the other.
In PCM mode, if the data for a given channel remains at a 0 level for 1024 sample periods (or PLRCK clock
periods), a zero detect condition exists for that channel.
In DSD mode, the zero detection is not available.
zero output flags
Given that a zero detect condition exists for one or more channels, the zero flag pins for those channels will be
set to a logic 1 state. There are zero flag pins for each channel, ZEROL (pin 14) and ZEROR (pin 13). These
pins can be used to operate external mute circuits, or used as status indicators for a microcontroller, audio signal
processor, or other digitally-controlled circuit.
The active polarity of zero flag outputs can be inverted by setting the ZREV bit of control register 22 to 1. The
reset default is active high output, or ZREV = 0.
infinite zero detect mute
Infinite zero detect mute is an internal logic function. This function is available in PCM mode only. The zero detect
mute can be enabled or disabled using the INZD bit of control register 18. The reset default is zero detect mute
disabled, INZD = 0. If the input data on L- and R-channels is countinuously and simultaneously zero for 1024
clocks of LRCK, the zero mute circuitry will immediately force the corresponding DAC output(s) to the bipolar
zero level, or 0.5V
CC
.
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