參數(shù)資料
型號(hào)： DSD1702E
英文描述： ENHANCED MULTIFORMAT, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER
中文描述： 增強(qiáng)的多格式，Δ-Σ，音頻數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù)： 15/28頁(yè)
文件大?。?/td> 417K
代理商： DSD1702E
DSD1702
SLES005A
–
JUNE 2001
–
REVISED FEBRUARY 2002
15
www.ti.com
register definitions (continued)
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 18
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
OVER
RSV
INZD
RSV
RSV
MUT2
MUT1
MUTx Soft Mute Control
:PCM/DSD Mode
Where, x = 1 or 2, corresponding to the DAC output V
OUT
L (x = 1) and V
OUT
R (x = 2).
Default value: 0
MUTx = 0
MUTx = 1
Mute disabled (default)
Mute enabled
The mute bits, MUT1 and MUT2, are used to enable or disable the soft mute function for the corresponding DAC
outputs, V
OUT
L and V
OUT
R. The soft mute function is incorporated into the digital attenuators. When mute is
disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1,
the digital attenuator for the corresponding output will be decreased from the current setting to infinite
attenuation, one attenuator step (0.5 dB) at a time. This provides
pop-free
muting of the DAC output.
By setting MUTx = 0, the attenuator will be incremented one step at a time to the previously programmed
attenuation level.
INZD Infinite Zero Detect Mute Control
:PCM Mode
Default value: 0
INZD = 0
INZD = 1
Infinite zero detect mute disabled (default)
Infinite zero detect mute disabled (default)
The INZD bit is used to enable or disable the zero detect mute function described in the zero flag and infinite
zero detect mute section in this data sheet. The zero detect mute function is independent of the zero flag output
operation, so enabling or disabling the INZD bit has no effect on the zero flag outputs (ZEROL and ZEROR).
OVER Oversampling Rate Control
:PCM Mode
Default value: 0
OVER = 0
OVER = 1
64x Oversampling for system clock
≥
256f
s
, and 32x Oversampling for system clock < 256 f
s
. (default)
128x Oversampling for system clock
≥
256f
s
, and 64x Oversampling for system clock < 256 f
s
.
Sets the oversampling rate of the delta-sigma D/A converters. The OVER = 1 setting is recommended when
the system clock is 128 f
s
or 192 f
s
.
RSV Reserved Bit
The RSV should be set to 0.
IDX[6:0] Register Index
Register 18: 10010
B
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DSD1702 ENHANCED MULTIFORMAT, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER
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