參數(shù)資料
型號: DSD1702E
英文描述: ENHANCED MULTIFORMAT, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER
中文描述: 增強(qiáng)的多格式,Δ-Σ,音頻數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù): 19/28頁
文件大?。?/td> 417K
代理商: DSD1702E
DSD1702
SLES005A
JUNE 2001
REVISED FEBRUARY 2002
19
www.ti.com
register definitions (continued)
DSD DSD Mode Control
Default value: 0
:PCM/DSD Mode
DSD = 0
DSD = 1
PCM mode (default)
DSD mode
The DSD bit allows the user to control the operation mode, PCM mode and DSD mode.
SRST System Reset
:PCM/DSD Mode
Default value: 0
SRST = 0
SRST = 1
Not operated (default)
DAC system is reset once
The SRST bit allows the user to reset DAC system. This function is same as the power on reset.
RSV Reserved Bit
The RSV should be set to 0.
IDX[6:0] Register Index
Register 22: 10110
B
analog outputs
The DSD1702 includes two independent output channels, V
OUT
L and V
OUT
R. These are unbalanced outputs,
each capable of driving 3.1 V
(pp)
typical into a 10-k
ac-coupled load. The internal output amplifiers for V
OUT
L
and V
OUT
R are biased to the dc common-mode (or bipolar zero) voltage, equal to V
CC
/ 2.
The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy
present at the DAC outputs due to the noise shaping characteristics of the delta-sigma D/A converters. The
frequency response of this filter is shown in Figure 10. By itself, this filter may not be enough to attenuate the
out-of-band noise to an acceptable level for many applications. An external low-pass filter is recommended to
provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the
Applications Information section of this data sheet.
60
50
40
30
20
10
0
10
100
1 k
10 k
100 k
1 M
10 M
R
ANALOG FILTER PERFORMANCE (100 Hz
10 MHz)
f
Frequency
Hz
Figure 10. Output Filter Frequency Response
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