參數(shù)資料
型號： DS2196LN
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PQFP100
封裝： LQFP-100
文件頁數(shù)： 97/160頁
文件大?。?/td> 559K
代理商： DS2196LN
DS2196
41 of 160
Table 6-3: TPOSB/TNEGB Data Source Select
TTDSS1
TTDSS0
Data Source
0
Pass tpos/tclk/tneg from the framer through to the
TPOSOB/TCLKOB/TNEGOB pins.
0
1
Force TPOSOB to source data from the BERT circuit. TNEGOB
is the frame sync pulse.
1
0
Force TPOSOB high. TNEGOB is the frame sync pulse.
1
Force TPOSOB and TNEGOB high.
Payload Loopback A
Payload Loopback When CCR1A.1 is set to a 1, the Framer/Formatter A will be forced into Payload
Loopback (PLB). Normally, this loopback is only enabled when ESF framing is being performed but can
be enabled also in D4 framing applications. In a PLB situation, the DS2196 will loop the 192 bits of
payload data (with BPVs corrected) from the receive section back to the transmit section. The FPS
framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the
DS2196. When PLB is enabled, the following will occur:
1. The TCLKOA signal will become synchronous with RCLKA instead of TCLKA.
2. Data will be transmitted from the TRING and TTIP pins synchronous with RCLKA instead of
TCLKA.
3. All of the receive side signals will continue to operate normally.
4. The TCHCLKA and TCHBLKA signals are forced low.
5. TX serial data into Formatter A is ignored.
Payload Loopback B
When CCR1B.1 is set to a 1, the Framer/Formatter B will be forced into Payload Loopback (PLB).
Normally, this loopback is only enabled when ESF framing is being performed but can be enabled also in
D4 framing applications. In a PLB situation, the DS2196 will loop the 192 bits of payload data (with
BPVs corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6
calculation, and the FDL bits are not looped back, they are reinserted by the DS2196. When PLB is
enabled, the following will occur:
1. The TCLKOB signal will become synchronous with RCLKIB instead of TCLKB.
2. Data will be transmitted from the TPOSOB and TNEGOB pins synchronous with RCLKIB instead of
TCLKB.
3. All of the receive side signals will continue to operate normally.
4. The TCHCLKB and TCHBLKB signals are forced low.
5. TX serial data into Formatter B is ignored.
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PDF描述
DS21FF44 DATACOM, FRAMER, PBGA300
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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