參數(shù)資料
型號: DS2196LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP100
封裝: LQFP-100
文件頁數(shù): 15/160頁
文件大?。?/td> 559K
代理商: DS2196LN
DS2196
111 of 160
RHIRA: RECEIVE HDLC INFORMATION REGISTER FRAMER A
(Address = 03 Hex)
RHIRB: RECEIVE HDLC INFORMATION REGISTER FRAMER B
(Address = A3 Hex)
(MSB)
(LSB)
RABT
RCRCE
ROVR
RVM
REMPTY
POK
CBYTE
OBYTE
SYMBOL
POSITION
NAME AND DESCRIPTION
RABT
RHIR.7
Abort Sequence Detected. Set whenever the HDLC
controller sees 7 or more 1’s in a row.
RCRCE
RHIR.6
CRC Error. Set when the CRC checksum is in error.
ROVR
RHIR.5
Overrun. Set when the HDLC controller has attempted to
write a byte into an already full receive FIFO.
RVM
RHIR.4
Valid Message. Set when the HDLC controller has detected
and checked a complete HDLC packet.
REMPTY
RHIR.3
Empty. A real–time bit that is set high when the receive FIFO
is empty.
POK
RHIR.2
Packet OK. Set when the byte available for reading in the
receive FIFO at RHFR is the last byte of a valid message (and
hence no abort was seen, no overrun occurred, and the CRC
was correct).
CBYTE
RHIR.1
Closing Byte. Set when the byte available for reading in the
receive FIFO at RHFR is the last byte of a message (whether
the message was valid or not).
OBYTE
RHIR.0
Opening Byte. Set when the byte available for reading in the
receive FIFO at RHFR is the first byte of a message.
NOTE:
The RABT, RCRCE, ROVR, and RVM bits are latched and will be cleared when read.
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