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參數(shù)資料
| 型號(hào)： | DS2196LN |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PQFP100 |
| 封裝： | LQFP-100 |
| 文件頁(yè)數(shù)： | 85/160頁(yè) |
| 文件大?。?/td> | 559K |
| 代理商： | DS2196LN |
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DS2196
30 of 160
5
PARALLEL PORT
The DS2196 is controlled via either a non-–multiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by
an external microcontroller or microprocessor. The DS2196 can operate with either Intel or Motorola bus
timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola
timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in
the AC Electrical Characteristics in Section 22 for more details.
6
CONTROL, ID, AND TEST REGISTERS
Each framer in the DS2196 is configured via a set of eleven control registers. Typically, the control
registers are only accessed when the system is first powered up. Once the DS2196 has been initialized,
the control registers will only need to be accessed when there is a change in the system configuration.
There are two Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and
TCR2), and seven Common Control Registers (CCR1 to CCR7).
Each of the eleven registers are
described in this section. There is a device Identification Register (IDR) at address 0Fh. The MSB of this
read–only register is fixed to a 0 indicating that a T1 device is present. The next 3 MSBs are used to
indicate which T1 device is present. The lower 4 bits of the IDR are used to display the die revision of
the chip.
Power–Up Sequence
The DS2196 does not automatically clear its register space on power–up. After the supplies are stable,
the register space should be configured for operation by writing to all of the internal registers. This
includes setting the Test and all unused registers to 00Hex.
This can be accomplished using a two-pass approach.
1. Clear DS2196 register space by writing 00h to the addresses 00h through 0FFh.
2. Program required registers to achieve desired operating mode.
IDR: DEVICE IDENTIFICATION REGISTER (Address = 0F Hex)
(MSB)
(LSB)
0011
ID3
ID2
ID1
ID0
SYMBOL
POSITION
NAME AND DESCRIPTION
0IDR.7
Chip ID Bit 3. MSB of DS2196 identification code. Set to 0.
0IDR.6
Chip ID Bit 2. DS2196 identification code. Set to 0.
1IDR.5
Chip ID Bit 1. DS2196 identification code. Set to 1.
1IDR.4
Chip ID Bit 0. LSB of DS2196 identification code. Set to 1.
ID3
IDR.3
Chip Revision Bit 3. MSB of a decimal code that represents
the chip revision.
ID2
IDR.1
Chip Revision Bit 2.
ID1
IDR.2
Chip Revision Bit 1.
ID0
IDR.0
Chip Revision Bit 0. LSB of a decimal code that represents the
chip revision.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21FF44 | DATACOM, FRAMER, PBGA300 |
| DS21FF44N | DATACOM, FRAMER, PBGA300 |
| DS21FT40N | DATACOM, FRAMER, PBGA300 |
| DS21FT40 | DATACOM, FRAMER, PBGA300 |
| DS21FT42 | DATACOM, FRAMER, PBGA300 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2196LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Dual Framer LIU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS219T | 功能描述:烙鐵 DESOLDERING HEAD RoHS:否 制造商:Weller 產(chǎn)品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included |
| DS21E352 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21E352N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21E354 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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