參數(shù)資料
型號(hào): DS2196LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP100
封裝: LQFP-100
文件頁數(shù): 11/160頁
文件大?。?/td> 559K
代理商: DS2196LN
DS2196
108 of 160
18.1.4 HDLC/BOC Register Description
HCRA: HDLC CONTROL REGISTER FRAMER A (Address = 00 Hex)
HCRB: HDLC CONTROL REGISTER FRAMER B (Address = A0 Hex)
(MSB)
(LSB)
RBR
RHR
TFS
THR
TABT
TEOM
TZSD
TCRCD
SYMBOL
POSITION
NAME AND DESCRIPTION
RBR
HCR.7
Receive BOC Reset. A 0 to 1 transition will reset the BOC
circuitry. Must be cleared and set again for a subsequent reset.
RHR
HCR.6
Receive HDLC Reset. A 0 to 1 transition will reset the HDLC
controller. Must be cleared and set again for a subsequent
reset.
TFS
HCR.5
Transmit Flag/Idle Select.
0 = 7Eh
1 = FFh
THR
HCR.4
Transmit HDLC Reset. A 0 to 1 transition will reset both the
HDLC controller and the transmit BOC circuitry. Must be
cleared and set again for a subsequent reset.
TABT
HCR.3
Transmit Abort. A 0 to 1 transition will cause the FIFO
contents to be dumped and one FEh abort to be sent followed
by 7Eh or FFh flags/idle until a new packet is initiated by
writing new data into the FIFO. Must be cleared and set again
for a subsequent abort to be sent.
TEOM
HCR.2
Transmit End of Message. Should be set to a 1 just before
the last data byte of a HDLC packet is written into the transmit
FIFO at THFR. The HDLC controller will clear this bit when
the last byte has been transmitted.
TZSD
HCR.1
Transmit Zero Stuffer Defeat. Overrides internal enable.
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
TCRCD
HCR.0
Transmit CRC Defeat.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
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