參數(shù)資料
型號: DS2196LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP100
封裝: LQFP-100
文件頁數(shù): 57/160頁
文件大?。?/td> 559K
代理商: DS2196LN
DS2196
15 of 160
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PIN FUNCTION DESCRIPTION
TRANSMIT SIDE PINS
Signal Name:
TCLKA/B
Signal Description:
Transmit Clock
Signal Type:
Input
A 1.544 MHz primary clock is applied here. Used to clock data through the transmit side formatters.
TCLKA/B can be internally connected to RCLKB/A via the CCR4B.2 control bit.
Signal Name:
TSERA/B
Signal Description:
Transmit Serial Data
Signal Type:
Input
Transmit NRZ serial data. Sampled on the falling edge of TCLKA or TCLKB. TSERA/B can be
internally connected to RSERB/A via the CCR4B.2 control bit.
Signal Name:
TSYNCA/B
Signal Description:
Transmit Sync
Signal Type:
Input / Output
When programmed as an input, a pulse at this pin will establish either frame or multiframe boundaries for
the transmit side. Via TCR2A.2 and TCR2B.2, the DS2196 can be programmed to output either a frame
or multiframe pulse at this pin. If this pin is set to output pulses at frame boundaries, it can also be set via
TCR2A.4 and TCR2B.4 to output double–wide pulses at signaling frames. See Section 21 for details.
TSYNCA/B can be internally connected to RMSYNCB/A via the CCR4B.2 control bit.
Signal Name:
TCHCLKA/B / TLCLKA/B
Signal Description:
Transmit Channel Clock / Transmit Link Clock
Signal Type:
Output
A dual function pin depending on the setting of the CCR4A.1 and CCR4B.1 control bits. If TCHCLK is
selected, a 192-kHz clock, which pulses high during the LSB of each channel, will be output. If TLCLK
is selected, either a 4 kHz or 2 kHz (ZBTSI) demand clock for the TLINK data is output. This output
signal is always synchronous with TCLKA or TCLKB. See Section 21 for details.
Signal Name:
TCHBLKA/B / TLINKA/B
Signal Description:
Transmit Channel Block / Transmit Link Data
Signal Type:
Input / Output
A dual function pin depending on the setting of the CCR4A.1 and CCR4B.1 control bits. If TCHBLK is
selected, a user programmable output that can be forced high or low during any of the 24 T1 channels is
output. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all T1
channels are used such as Fractional T1, 384 kbps service, 768 kbps, or ISDN–PRI. Also useful for
locating individual channels in drop–and–insert applications, for external per–channel loopback, and for
per–channel conditioning. See Section 21 for details. If TLINK is selected, this pin will be sampled on
the falling edge of TCLKA or TCLKB for data insertion into either the FDL stream (ESF) or the Fs–bit
position (D4) or the Z–bit position (ZBTSI).
See Section 21 for details.
This signal is always
synchronous with TCLKA or TCLKB.
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