參數(shù)資料
型號: DS2196LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP100
封裝: LQFP-100
文件頁數(shù): 146/160頁
文件大?。?/td> 559K
代理商: DS2196LN
DS2196
86 of 160
RSCD2A: RECEIVE SPARE CODE DEFINITION REGISTER 2 FRAMER A
(Address = 1C Hex)
RSCD2B: RECEIVE SPARE CODE DEFINITION REGISTER 2 FRAMER B
(Address = BC Hex)
(MSB)
(LSB)
C7
C6
C5
C4
C3
C2
C1
C0
SYMBOL
POSITION
NAME AND DESCRIPTION
C7
RSCD2.7
Receive Spare Code Definition Bit 7. A Don’t Care if a 1 to
7 bit length is selected.
C6
RSCD2.6
Receive Spare Code Definition Bit 6. A Don’t Care if a 1 to
7 bit length is selected.
C5
RSCD2.5
Receive Spare Code Definition Bit 5. A Don’t Care if a 1 to
7 bit length is selected.
C4
RSCD2.4
Receive Spare Code Definition Bit 4. A Don’t Care if a 1 to
7 bit length is selected.
C3
RSCD2.3
Receive Spare Code Definition Bit 3. A Don’t Care if a 1 to
7 bit length is selected.
C2
RSCD2.2
Receive Spare Code Definition Bit 2. A Don’t Care if a 1 to
7 bit length is selected.
C1
RSCD2.1
Receive Spare Code Definition Bit 1. A Don’t Care if a 1 to
7 bit length is selected.
C0
RSCD2.0
Receive Spare Code Definition Bit 0. A Don’t Care if a 1 to
7 bit length is selected.
13
CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking
Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively.
The
RCHBLK and TCHBLK pins are user programmable outputs that can be forced either high or low during
individual channels. These outputs can be used to block clocks to a UART or LAPD controller in
Fractional T1 or ISDN–PRI applications. When the appropriate bits are set to a 1, the RCHBLK and
TCHBLK pins will be held high during the entire corresponding channel time.
See the timing in
Section 21 for an example.
相關PDF資料
PDF描述
DS21FF44 DATACOM, FRAMER, PBGA300
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DS21FT42 DATACOM, FRAMER, PBGA300
相關代理商/技術參數(shù)
參數(shù)描述
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