參數(shù)資料
型號(hào): DS21348GN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, BGA49
封裝: CABGA-49
文件頁數(shù): 30/44頁
文件大小: 1078K
代理商: DS21348GN
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
36
I 2C Write Operation
The MAX8660/MAX8661 are write-only devices and
recognize the “write byte” protocol as defined in the
SMBus specification and shown in section A of Figure
11. The “write byte” protocol allows the I2C master
device to send 1 byte of data to the slave device. The
“write byte” protocol requires a register pointer address
for the subsequent write. The MAX8660/MAX8661
acknowledge any register pointer even though only a
subset of those registers actually exists in the device.
The “write byte” protocol is as follows:
1) The master sends a start command.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave updates with the new data.
8) The slave acknowledges the data byte.
9) The master sends a STOP condition.
In addition to the write-byte protocol, the MAX8660/
MAX8661 recognize the multiple byte register-data pair
protocol as shown in section B of Figure 11. This proto-
col allows the I2C master device to address the slave
only once and then send data to multiple registers in a
random order. Registers may be written continuously
until the master issues a STOP condition.
The multiple-byte register-data pair protocol is as
follows:
1) The master sends a start command.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave updates with the new data.
8) The slave acknowledges the data byte.
9) Steps 5 to 7 are repeated as many times as
the master requires. Registers may be accessed in
random order.
10)The master sends a STOP condition.
REGISTER
ADDRESS
REGISTER
NAME
BIT
NAME
FUNCTION
7MVS
V5 (VCC_MVT) voltage select:
0—Ramp V5 to voltage selected by MDTV1 (default)
1—Ramp V5 to voltage selected by MDTV2
6
MGO
Start V5 (VCC_MVT) voltage change:
0—Hold V5 at current level (default)
1—Ramp V5 as selected by MVS
5
SVS
V4 (VCC_SRAM) voltage select:
0—Ramp V4 to voltage selected by SDTV1 (default)
1—Ramp V4 to voltage selected by SDTV2
4
SGO
Start V4 (VCC_SRAM) voltage change:
0—Hold V4 at current level (default)
1—Ramp V4 as selected by SVS
3
R
Reserved
2
R
Reserved
1
AVS
V3 (VCC_APPS) voltage select:
0—Ramp V3 to voltage selected by ADTV1 (default)
1—Ramp V3 to voltage selected by ADTV2
0x20
VCC1
0
AGO
Start V3 (VCC_APPS) voltage change:
0—Hold V3 at current level (default)
1—Ramp V3 as selected by AVS
Table 10. DVM Voltage-Change Register (VCC1, 0x20)
相關(guān)PDF資料
PDF描述
DS21348T DATACOM, PCM TRANSCEIVER, PQFP44
DS21348TN DATACOM, PCM TRANSCEIVER, PQFP44
DS21348G DATACOM, PCM TRANSCEIVER, BGA49
DS21Q348N DATACOM, PCM TRANSCEIVER, PBGA144
DS21Q348 DATACOM, PCM TRANSCEIVER, PBGA144
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