參數(shù)資料
型號(hào): DS21348GN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, BGA49
封裝: CABGA-49
文件頁(yè)數(shù): 28/44頁(yè)
文件大小: 1078K
代理商: DS21348GN
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
34
DATA
BIT
REGISTER
ADDRESS
REGISTER
NAME
R/W
FUNCTION
76
5
4
3
2
1
0
RR
R
EN4
(S_EN)
R
EN3
(A_EN)
0x10
OVER1*
W
Output-Voltage
Enable
Register
1.
Enables/disables
V3
and
V4.
See
the
REG3/REG4
Enable
(EN34,
EN3,
EN4)
section
for
more
information.
Default
0
R—
EN7**
EN6
0x12
OVER2
W
Output-Voltage
Enable
Register
2.
Enables/disables
V6
and
V7.
See
the
REG6/REG7
(VCC_CARD1,
VCC_CARD2)
section
for
more
information.
Default
0
MVS
MGO
SVS
SGO
RR
AVS
AGO
0x20
VCC1*
W
Voltage-Change
Control
Register.
Independently
specifies
that
the
V3,
V4,
and
V5
output
voltage
must
follow
either
target
register
1
or
2.
See
Table
10
.
Default
0
RR
R
V3
(VCC_APPS)
Target
1
—See
Table
11
0x23
ADTV1*
W
VCC_APPS
(V3)
DVM
Target
Voltage
1
Register.
Sets
target
1
voltage
for
V3.
Default
0
1
0
1
RR
R
V3
(VCC_APPS)
Target
2
—See
Table
11
0x24
ADTV2*
W
VCC_APPS
(V3)
DVM
Target
Voltage
2
Register.
Sets
target
2
voltage
for
V3.
Default
0
1
0
1
RR
R
V4
(VCC_SRAM)
Target
1
—See
Table
11
0x29
SDTV1*
W
VCC_SRAM
(V4)
DVM
Target
Voltage
1
Register.
Sets
target
1
voltage
for
V4.
Default
0
1
0
1
RR
R
V4
(VCC_SRAM)
Target
2
—See
Table
11
0x2A
SDTV2*
W
VCC_SRAM
(V4)
DVM
Target
Voltage
2
Register.
Sets
target
2
voltage
for
V4.
Default
0
1
0
1
RR
R
V5
(VCC_MVT)
Target
1
—See
Table
12
0x32
MDTV1
W
VCC_MVT
(V5)
Target
Voltage
1
Register.
Sets
target
1
voltage
for
V5.
Default
0
1
0
RR
R
V5
(VCC_MVT)
Target
2
—See
Table
12
0x33
MDTV2
W
VCC_MVT
(V5)
DVM
Target
Voltage
2
Register.
Sets
target
2
voltage
for
V5.
Default
0
1
0
V7
Voltage
—See
Table
13
V6
Voltage
—See
Table
13
0x39
L12VCR
W
LDO1
and
LDO2
Voltage-Control
Register
(V6
and
V7
on
MAX8660).
Specifies
the
V6
and
V7
output
voltage.
V6
and
V7
are
enabled/disabled
with
OVER2.
Default
0
ARD4
ARD3
——
FPWM4
FPWM3
FPWM2
FPWM1**
0x80
FPWM
W
Forced-PWM
Register.
The
FPWM_
bits
allow
V1,
V2,
V3,
and
V4
to
independently
operate
in
either
skip
mode
or
forced-
PWM
mode.
See
the
REG1–REG4
Step-Down
DC-DC
Converter
Operating
Modes
section
for
more
information.
The
ARD_
bits
allow
the
output
voltage
to
be
actively
ramped
down
during
negative
voltage
transitions
See
the
Ramp-Rate
Control
(RAMP)
section
for
more
information.
Note
that
this
is
a
Maxim
custom
register
that
is
not
required
by
the
Marvell
PXA3xx
processor.
Default
0
Table
9.
I
2
C
Registers
R
means
these
data
locations
are
designated
reserved
in
the
Marvell
PXA3xx
specification.
Note:
The
MAX8660/MAX8661
acknowledge
attempts
to
write
to
the
entire
address
space
from
0x00
to
0xFF,
even
though
only
a
subset
of
t
hose
addresses
actually
exist
in
the
IC.
*These
registers
are
accessed
by
the
power
I
2
C
bus
of
the
Marvell
PXA3xx
processor.
**
Maintain
these
bits
at
their
default
0
value
for
the
MAX8661.
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