參數(shù)資料
型號(hào)： DS21348GN
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Interface
英文描述： DATACOM, PCM TRANSCEIVER, BGA49
封裝： CABGA-49
文件頁(yè)數(shù)： 22/44頁(yè)
文件大?。?/td> 1078K
代理商： DS21348GN
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
29
Table 5. Enable Signals
MAXIM ENABLE SIGNAL
POWER DOMAIN
HARDWARE
SOFTWARE
APPLICATIONS PROCESSOR
ENABLE SIGNAL
V1 (VCC_IO) (MAX8660/MAX8660A only)
EN1
—
V2 (VCC_MEM)
EN2
—
V5 (VCC_MVT)
EN5
—
SYS_EN
V3 (VCC_APPS)
EN3 (OVER1)
V4 (VCC_SRAM)
EN34
EN4 (OVER1)
PWR_EN &
PWR_I2C
V6 (VCC_CARD1)
—
EN6 (OVER2)
V7 (VCC_CARD2) (MAX8660/MAX8660A only)
—
EN7 (OVER2)
Standard I2C
V8 (VCC_BBATT)
Always on
—
between RRAMP and the output-voltage ramp rates. A
56k
RRAMP satisfies the typical requirements of
Marvell PXA3xx processors; 200s after being enabled,
REG3 and REG4 linearly ramp from 0V to the set output
voltage at the rate set by RRAMP. When REG3 and
REG4 are disabled, the output voltage decays at a rate
determined by the output capacitance, internal 550
discharge resistance, and the external load.
Active ramp-down functionality is inherent in forced-
PWM operation. In normal-mode operation, active ramp
down is enabled by setting ARD3 and ARD4 (Table 9).
With “active ramp-down” enabled, the regulator output
voltage ramps down at the rate set by RRAMP. With small
loads, the regulator must sink current from the output
capacitor to actively ramp down the output voltage. In
normal mode, with “active ramp-down” disabled, the
regulator output voltage ramps down at the rate deter-
mined by the output capacitance and the external load;
small loads result in an output-voltage decay that is slow-
er than that specified by RRAMP, large loads (> COUT x
RAMPRATE) result in an output-voltage decay that is no
faster than that specified by RRAMP.
80s after being enabled, REG5 linearly ramps from 0V
to the set output voltage in 225s. The ramp rate during
a positive voltage change (i.e., 1.8V to 1.9V) is set with
RRAMP. During a negative voltage change (i.e., 1.9V to
1.8V), the REG5 output voltage decays at a rate deter-
mined by the output capacitance and the external load;
however, ramp-down is no faster than the rate specified
by RRAMP. When REG5 is disabled, the output voltage
decays at a rate determined by the output capacitance,
internal 2k
discharge resistance, and the external load.
60s after being enabled by I2C, REG6 and REG7 lin-
early ramp from 0V to the set output voltage in 450s.
REG6 and REG7 do not have positive voltage-change
(i.e., 1.8V to 2.5V) ramp-rate control. During a positive
voltage change, the output-voltage dV/dt is as fast as
possible. To avoid this fast output dV/dt, disable REG6
or REG7 before changing the output. With this method,
the soft-start ramp rate limits the output dV/dt, and
therefore, the input current is controlled. During a nega-
tive voltage change (i.e., 2.5V to 1.8V), the REG6 or
REG7 output voltage decays at a rate determined by
the output capacitance and the external load. When
REG6 or REG7 is disabled, the output voltage decays
at a rate determined by the output capacitance, internal
350
discharge resistance, and the external load.
Power Sequencing
Enable Signals (EN_, PWR_EN, SYS_EN, I2C)
As shown in Table 5, the MAX8660/MAX8661 feature
numerous enable signals for flexibility in many applica-
tions. In a typical application with the Marvell PXA3xx
processor, many of these enable signals are connected
together. EN1, EN2, and EN5 typically connect to the
SYS_EN output. With this connection, REG5 is the first
supply to rise (if IN5 is connected to IN). EN34 typically
connects to Marvell’s
PWR_EN output. Alternatively,
REG3 and REG4 can be activated by the I2C interface
(see the
REG3/REG4 Enable (EN34, EN3, EN4) section
for more information). REG6 and REG7 are activated by
the serial interface. REG8 has no enable input and
always remains on as long the MAX8660/MAX8661 are
powered between the UVLO and OVLO range. All regu-
lators are forced off during UVLO and OVLO. See the
Undervoltage and Overvoltage Lockout section for
more information.
Note: The logic that controls the Marvell PXA3xx
processor
SYS_EN and PWR_EN signals is powered
from the
VCC_BBATT power domain.
相關(guān)PDF資料
PDF描述
DS21348T DATACOM, PCM TRANSCEIVER, PQFP44
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DS21348G DATACOM, PCM TRANSCEIVER, BGA49
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21348GN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348GNB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348GN-C01 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348T 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21348T+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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