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參數(shù)資料
| 型號(hào)： | DS1963L-F5 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Memory IC:Other |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, MEDB2 |
| 封裝： | MICROCAN-2 |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 482K |
| 代理商： | DS1963L-F5 |
DS1963L
8 of 24
ADDRESS REGISTERS Figure 6
T7
T6
T5
T4
T3
T2
T1
T0
T15
T14
T13
T12
T11
T10
T9
T8
AA
1)
PF
E4
E3
E2
E1
E0
1)
THIS BIT WILL ALWAYS BE 0.
Read Memory + Counter [A5H]
The Read Memory + Counter command is used to read memory data together with the write cycle counter
associated with the addressed page of data memory. The additional information is transmitted by the
DS1963L as the end of a memory page is encountered. Following the current value of the page write
cycle counter the DS1963L transmits 32 tamper-detect bits and a 16-bit CRC generated by the DS1963L.
The tamper-detect bits are factory-preset to 55555555H and locked. Tampering with the device will
change this data pattern.
After having sent the command code of the Read Memory + Counter command, the bus master sends a 2-
byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field.
With the subsequent read data time slots the master receives data from the DS1963L starting at the initial
address and continuing until the end of a 32-byte page is reached. At that point the bus master will send
80 additional read data time slots and receive the contents of the 32-bit write cycle counter associated
with the addressed page, the status of the 32 tamper-detect bits and a 16-bit CRC. With subsequent read
data time slots the master will receive data starting at the beginning of the next page followed again by
the contents of the page write cycle counter, tamper-detect bits and CRC for that page. This sequence will
continue until the final page and its accompanying data are read by the bus master. When applying the
Read Memory + Counter command to a page that does not have a page write cycle counter associated, the
master will read FFFFFFFFH instead of a valid cycle count.
With the initial pass through the Read Memory + Counter flow chart the 16-bit CRC value is the result of
shifting the command byte into the cleared CRC generator, followed by the 2 address bytes, the contents
of the data memory, the write page cycle counter and the tamper-detect bits. Subsequent passes through
the Read Memory + Counter flow chart will generate a 16-bit CRC that is the result of clearing the CRC
generator and then shifting in the contents of the data memory page, its associated page write cycle
counter and tamper-detect bits. After the 16-bit CRC of the last page is read, the bus master will receive
logical 1’s from the DS1963L until a Reset Pulse is issued. The Read Memory + Counter command
sequence can be ended at any point by issuing a Reset Pulse.
TARGET ADDRESS (TA1)
TARGET ADDRESS (TA2)
ENDING ADDRESS WITH
DATA STATUS (E/S)
(READ ONLY)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1963S | SPECIALTY MEMORY CIRCUIT, MEDB2 |
| DS1985-F3 | 2K X 8 EEPROM 3V, RDB2 |
| DS1986-F3 | 64K X 1 OTPROM, MEDB2 |
| DS1986-F5 | 64K X 1 OTPROM, MADB2 |
| DS1991L-F5 | SPECIALTY MEMORY CIRCUIT, MEDB2 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1963L-F5+ | 功能描述:iButton RoHS:否 存儲(chǔ)類型:SRAM 存儲(chǔ)容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated |
| DS1963L-F5+W | 功能描述:iButton RoHS:否 存儲(chǔ)類型:SRAM 存儲(chǔ)容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated |
| DS1963R-F5+ | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube |
| DS1963S | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:SHA iButton |
| DS1963S+F5 | 制造商:Maxim Integrated Products 功能描述:SHA IBTN 8SOIC - Rail/Tube |
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