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DS1963L
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READ/WRITE TIMING DIAGRAM Figure 11 cont’d
Read-data Time Slot
Regular Speed
Overdrive Speed
60
s ≤ t
SLOT < 120 s6 s ≤ tSLOT < 16 s
1
s ≤ t
LOWR < 15 s1s ≤ tLOWR < 2 s
0
≤ t
RELEASE < 45 s0 ≤ t RELEASE < 4 s
1
s ≤ t
REC < ∞
1
s ≤ t
REC < ∞
tRDV = 15 stRDV = 2 s
tSU < 1stSU < 1s
CRC GENERATION
With the DS1963L there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is an 8-
bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC
value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS1963L to
determine if the ROM data has been received error-free by the bus master. The equivalent polynomial
function of this CRC is: X
8 + X5 + X4 + 1. This 8-bit CRC is received in the true (non-inverted) form when
reading the ROM of the DS1963L. It is computed at the factory and lasered into the ROM.
The other CRC is a 16-bit type, generated according to the standardized CRC16-polynomial function x
16 +
x
15 + x2 + 1. This CRC is used for error detection when reading Data Memory using the Read Memory +
Counter command and for fast verification of a data transfer when writing to the scratchpad. It is the same
type of CRC as is used with NV RAM-based iButtons for error detection within the iButton Extended
File Structure. In contrast to the 8-bit CRC, the 16-bit CRC is always returned or sent in the
complemented (inverted) form. A CRC-generator inside the DS1963L chip (Figure 12) will calculate a
new 16-bit CRC as shown in the command flow chart of Figure 7. The bus master compares the CRC
value read from the device to the one it calculates from the data and decides whether to continue with an
operation or to re-read the portion of the data with the CRC error.
With the initial pass through the Read Memory + Counter flow chart the 16-bit CRC value is the result of
shifting the command byte into the cleared CRC generator, followed by the 2 address bytes, the data
bytes, value of the page write cycle counter and tamper-detect bits. Subsequent passes through the Read
Memory + Counter flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator
and then shifting in the data bytes, the value of the page write cycle counter and the tamper-detect bits.
With the Write Scratchpad command the CRC is generated by first clearing the CRC generator and then
shifting in the command code, the Target Addresses TA1 and TA2 and all the data bytes. The DS1963L
will transmit this CRC only if the data bytes written to the scratchpad include scratchpad ending offset
11111b. The data may start at any location within the scratchpad.
For more details on generating CRC values including example implementations in both hardware and
software, see the “Book of DS19xx iButton Standards.”
RESISTOR
MASTER
DS1963L