參數資料
型號: DS1875T+
廠商: Maxim Integrated Products
文件頁數: 81/92頁
文件大?。?/td> 0K
描述: IC SFP CTRLR/TRIPLEXER 38-TQFN
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 90
應用: 光纖
接口: I²C
電源電壓: 2.85 V ~ 3.9 V
封裝/外殼: 38-WFQFN 裸露焊盤
供應商設備封裝: 38-TQFN(5x7)
包裝: 管件
安裝類型: 表面貼裝
產品目錄頁面: 1431 (CN2011-ZH PDF)
DS1875
PON Triplexer and SFP Controller
82
______________________________________________________________________________________
Table 02h, Register C5h to C6h: RESERVED
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
These registers are reserved.
Table 02h, Register C7h: M4 LUT CNTL
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
C7h
RESERVED
FBOL
FBCL
DBL_SB
UP_LOWB
BIT 7
BIT 0
BITS 7:4
RESERVED (Default = 000000b)
BITS 3:2
FBOL and FBCL: Force bias open loop and force bias closed loop.
00b = (Default) normal operation.
10b = Force control of IBIAS to be open loop regardless of duration of BEN pulses.
01b = Force control of IBIAS to be closed loop regardless of duration of BEN pulses.
11b = Same as 10b.
When forcing open-loop mode, BEN should be ground or at any burst length.
BIT 1
DBL_SB: Chooses the size of LUT for Table 06h.
0 = (Default) Single LUT of 32 bytes.
1 = Double LUT of 16 bytes.
BIT 0
UP_LOWB: Determines which 16-byte LUT is used if DBL_SB = 1. If DBL_SB = 0, the value of
this bit is a don’t care.
0 = (Default) Chooses the lower 16 bytes of Table 06h (80h to 8Fh).
1 = Chooses the upper 16 bytes of Table 06h (90h to 9Fh).
Controls the size and location of LUT functions for the MON4 measurement.
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