參數(shù)資料
型號(hào): DS1875T+
廠商: Maxim Integrated Products
文件頁數(shù): 51/92頁
文件大?。?/td> 0K
描述: IC SFP CTRLR/TRIPLEXER 38-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
應(yīng)用: 光纖
接口: I²C
電源電壓: 2.85 V ~ 3.9 V
封裝/外殼: 38-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 38-TQFN(5x7)
包裝: 管件
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 1431 (CN2011-ZH PDF)
DS1875
Lower Memory, Register 79h: DIN
POWER-ON VALUE
See description
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
79h
INV M3QT
MUX M3QT
INV LOS
MUX LOS
D3 IN
D2 IN
D1 IN
D0 IN
BIT 7
BIT 0
BIT 7
INV M3QT: Status of inversion of M3QT (internal signal) to D2 pin. MUX M3QT bit must be set to 1 or
this bit does not affect the output. The value is controlled (or set) by the DPU byte.
1 = M3QT buffered to D2 is inverted.
BIT 6
MUX M3QT: Determines control of D2 pin. The value is controlled (or set) by the DPU byte.
0 = Logic value of D2 is controlled by DOUT byte.
1 = Logic value of D2 is controlled by M3QT (internal signal) and INV M3QT bit.
BIT 5
INV LOS: Status of inversion of LOSI pin to D0 pin. MUX LOS bit must be set to 1 or this bit does not
effect the output. The value is controlled (or set) by the DPU byte.
1 = LOSI buffered D0 is inverted.
BIT 4
MUX LOS: Determines control of D0 pin. The value is controlled (or set) by the DPU byte.
0 = Logic value of D0 is controlled by DOUT byte.
1 = Logic value of D0 is controlled by LOSI pin and INV LOS bit.
BIT 3
D3 IN: Reflects the logic value of D3 pin.
BIT 2
D2 IN: Reflects the logic value of D2 pin.
BIT 1
D1 IN: Reflects the logic value of D1 pin.
BIT 0
D0 IN: Reflects the logic value of D0 pin.
Lower Memory, Register 7Ah: RESERVED
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
N/A
This register is reserved. The value when read is 00h.
PON Triplexer and SFP Controller
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