參數(shù)資料
型號(hào): DS1875T+
廠商: Maxim Integrated Products
文件頁數(shù): 13/92頁
文件大?。?/td> 0K
描述: IC SFP CTRLR/TRIPLEXER 38-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
應(yīng)用: 光纖
接口: I²C
電源電壓: 2.85 V ~ 3.9 V
封裝/外殼: 38-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 38-TQFN(5x7)
包裝: 管件
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 1431 (CN2011-ZH PDF)
DS1875
PON Triplexer and SFP Controller
20
______________________________________________________________________________________
The ADC results (after right-shifting, if used) are com-
pared to high and low alarm and warning thresholds
after each conversion. The alarm values can be used to
trigger the TX-F or FETG outputs. These ADC thresholds
are user programmable through the I2C interface, as
well as masking registers that can be used to prevent
the alarms from triggering the TX-F and FETG outputs.
ADC Timing
There are 10 analog channels that are digitized in a
sequential fashion. The MON5–MON8 channels are
sampled depending on the state of the EN5TO8B bit in
Table 02h, Register 89h. If the bit is programmed to
logic 0, the ADC cycles through temperature, VCC, and
MON1–MON4 (Figure 5). If the bit is programmed to
logic 1, all 10 channels are digitized, including chan-
nels MON5–MON8 (Figure 6). In this mode (EN5TO8B
= 0), each of MON5–MON8 is sampled on alternate
cycles, as shown in Figure 5. The total time required to
convert one set of channels is the sequential ADC
cycle time, tFRAME1 or tFRAME2 (see Figure 6).
Table 3. ADC Default Monitor Ranges
SIGNAL
+FS
SIGNAL
+FS
HEX
-FS
SIGNAL
-FS
HEX
Temperature (°C)
127.996
7FFF
-128
8000
VCC (V)
6.5528
FFF8
0
0000
MON1–MON8 (V)
2.4997
FFF8
0
0000
VCC
MON1
MON2
MON3
MON4
MON5
MON6
TEMP
VCC
MON1
MON2
MON3
MON4
MON7
MON8
TEMP
tFRAME2
Figure 6. ADC Timing with EN5TO8B = 1
TEMP
VCC
MON1
MON2
MON3
MON4
TEMP
ONE ADC CYCLE
MON4
tFRAME1
Figure 5. ADC Timing with EN5TO8B = 0
TRIP CONDITION
mCLK
(525kHz)
CAPTURE ALARM
M3QT ALARM
(UNLATCHED)
Figure 4. M3QT Timing
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