參數(shù)資料
型號: DS1875T+
廠商: Maxim Integrated Products
文件頁數(shù): 50/92頁
文件大小: 0K
描述: IC SFP CTRLR/TRIPLEXER 38-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 90
應(yīng)用: 光纖
接口: I²C
電源電壓: 2.85 V ~ 3.9 V
封裝/外殼: 38-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 38-TQFN(5x7)
包裝: 管件
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 1431 (CN2011-ZH PDF)
DS1875
PON Triplexer and SFP Controller
54
______________________________________________________________________________________
Lower Memory, Register 78h: DOUT
POWER-ON VALUE
Recalled from Table 02h, Register C0h
READ ACCESS
All
WRITE ACCESS
All
MEMORY TYPE
Volatile
78h
M3QT
RESET
SOFT
M3QT
RESERVED
D3 OUT
D2 OUT
D1 OUT
D0 OUT
BIT 7
BIT 0
BIT 7
M3QT RESET: Resets the latch for M3QT. The PWM does not begin normal operation until the MON3
voltage is below M3QT, regardless of resetting the latch.
0 = (default)
1 = M3QT alarm is reset.
BIT 6
SOFT M3QT: Software control for setting the M3QT alarm. The PWM output pulse SW is disabled.
0 = (Default) Internal signal is controlled by trip point comparison.
1 = M3QT alarm is set to 1.
BITS 5:4
RESERVED
BIT 3
D3 OUT: Controls the output of the open-drain pin D3.
0 = Output is held low.
1 = Output is high impedance.
BIT 2
D2 OUT: Controls the output of the open-drain pin D2.
0 = Output is held low.
1 = Output is high impedance.
BIT 1
D1 OUT: Controls the output of the open-drain pin D1.
0 = Output is held low.
1 = Output is high impedance.
BIT 0
D0 OUT: Controls the output of the open-drain pin D0.
0 = Output is held low.
1 = Output is high impedance.
At power-on, these bits are defined by the value stored in the DPU byte (Table 02h, Register C0h). These bits define
the value of the logic states of their corresponding output pins.
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