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| 型號(hào)： | DP83848HSQ/NOPB |
| 廠(chǎng)商： | National Semiconductor |
| 文件頁(yè)數(shù)： | 39/82頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETHERNET PHYTER 40-LLP |
| 產(chǎn)品培訓(xùn)模塊： | PHYTER® Family |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | 以太網(wǎng) |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 40-LLP-EP（6x6） |
| 包裝： | 剪切帶 (CT) |
| 配用： | DP83848H-MAU-EK-ND - BOARD EVALUATION DP83848H |
| 其它名稱(chēng)： | *DP83848HSQ/NOPB DP83848HSQCT |
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DP
83
84
8
H
The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848H. The Identifier consists of a
concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num-
ber. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended
to support network management. National's IEEE assigned OUI is 080017h.
7.1.3 PHY Identifier Register #1 (PHYIDR1)
7.1.4 PHY Identifier Register #2 (PHYIDR2)
7.1.5 Auto-Negotiation Advertisement Register (ANAR)
This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Nego-
tiation. Any writes to this register prior to completion of Auto-Negotiation (as indicated in the Basic Mode Status Register
(address 0x01) Auto-Negotiation complete bit, BMSR[5] ) should be followed by a renegotiation. This will ensure that the
new values are properly used in the Auto-Negotiation.
Table 14. PHY Identifier Register #1 (PHYIDR1), address 0x02
Bit
Bit Name
Default
Description
15:0
OUI_MSB
<0010 0000 0000
0000>, RO/P
OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are
stored in bits 15 to 0 of this register. The most significant two bits
of the OUI are ignored (the IEEE standard refers to these as bits 1
and 2).
Table 15. PHY Identifier Register #2 (PHYIDR2), address 0x03
Bit
Bit Name
Default
Description
15:10
OUI_LSB
<0101 11>, RO/P OUI Least Significant Bits:
Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10
of this register respectively.
9:4
VNDR_MDL
<00 1001>, RO/P Vendor Model Number:
The six bits of vendor model number are mapped from bits 9 to 4
(most significant bit to bit 9).
3:0
MDL_REV
<0000>, RO/P
Model Revision Number:
Four bits of the vendor model revision number are mapped from
bits 3 to 0 (most significant bit to bit 3). This field will be incremented
for all major device changes.
Table 16. Negotiation Advertisement Register (ANAR), address 0x04
Bit
Bit Name
Default
Description
15
NP
0, RW
Next Page Indication:
0 = Next Page Transfer not desired.
1 = Next Page Transfer desired.
14
RESERVED
0, RO/P
RESERVED by IEEE: Writes ignored, Read as 0.
13
RF
0, RW
Remote Fault:
1 = Advertises that this device has detected a Remote Fault.
0 = No Remote Fault detected.
12
RESERVED
0, RW
RESERVED for Future IEEE use: Write as 0, Read as 0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DP83848I | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Industrial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver |
| DP83848I_08 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:PHYTER? - Industrial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver |
| DP83848I-MAU-EK | 功能描述:BOARD EVALUATION DP83848I RoHS:否 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| DP83848I-MAU-EK/NOPB | 功能描述:以太網(wǎng)開(kāi)發(fā)工具 DP83848 MAU CARD IND TEMP RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類(lèi)型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類(lèi)型:RMII 工作電源電壓: |
| DP83848I-POE-EK | 功能描述:以太網(wǎng)開(kāi)發(fā)工具 DP83848 POE CARD IND TEMP RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類(lèi)型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類(lèi)型:RMII 工作電源電壓: |
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