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參數(shù)資料
| 型號： | DP83848HSQ/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 26/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETHERNET PHYTER 40-LLP |
| 產(chǎn)品培訓模塊： | PHYTER® Family |
| 標準包裝： | 1 |
| 類型： | 收發(fā)器 |
| 驅動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | 以太網(wǎng) |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 40-LLP-EP（6x6） |
| 包裝： | 剪切帶 (CT) |
| 配用： | DP83848H-MAU-EK-ND - BOARD EVALUATION DP83848H |
| 其它名稱： | *DP83848HSQ/NOPB DP83848HSQCT |
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4.3.6 Jabber Function
The jabber function monitors the DP83848H's output and
disables the transmitter if it attempts to transmit a packet
of longer than legal size. A jabber timer monitors the
transmitter and disables the transmission if the transmitter
is active for approximately 85 ms.
Once disabled by the Jabber function, the transmitter
stays disabled for the entire time that the ENDEC mod-
ule's internal transmit enable is asserted. This signal has
to be de-asserted for approximately 500 ms (the “unjab”
time) before the Jabber function re-enables the transmit
outputs.
The Jabber function is only relevant in 10BASE-T mode.
4.3.7 Automatic Link Polarity Detection and
Correction
The DP83848H's 10BASE-T transceiver module incorpo-
rates an automatic link polarity detection circuit. When
three consecutive inverted link pulses are received, bad
polarity is reported.
A polarity reversal can be caused by a wiring error at
either end of the cable, usually at the Main Distribution
Frame (MDF) or patch panel in the wiring closet.
The bad polarity condition is latched in the 10BTSCR reg-
ister. The DP83848H's 10BASE-T transceiver module cor-
rects for this error internally and will continue to decode
received data correctly. This eliminates the need to correct
the wiring error immediately.
4.3.8 Transmit and Receive Filtering
External 10BASE-T filters are not required when using the
DP83848H, as the required signal conditioning is inte-
grated into the device.
Only isolation transformers and impedance matching
resistors are required for the 10BASE-T transmit and
receive interface. The internal transmit filtering ensures
that all the harmonics in the transmit signal are attenuated
by at least 30 dB.
4.3.9 Transmitter
The encoder begins operation when the Transmit Enable
input (TX_EN) goes high and converts NRZ data to pre-
emphasized Manchester data for the transceiver. For the
duration of TX_EN, the serialized Transmit Data (TXD) is
encoded for the transmit-driver pair (PMD Output Pair).
TXD must be valid on the rising edge of Transmit Clock
(TX_CLK). Transmission ends when TX_EN deasserts.
The last transition is always positive; it occurs at the cen-
ter of the bit cell if the last bit is a one, or at the end of the
bit cell if the last bit is a zero.
4.3.10 Receiver
The decoder detects the end of a frame when no addi-
tional mid-bit transitions are detected. Within one and a
half bit times after the last bit, carrier sense is de-asserted.
Receive clock stays active for five more bit times after
CRS goes low, to guarantee the receive timings of the
controller.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DP83848I | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Industrial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver |
| DP83848I_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PHYTER? - Industrial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver |
| DP83848I-MAU-EK | 功能描述:BOARD EVALUATION DP83848I RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| DP83848I-MAU-EK/NOPB | 功能描述:以太網(wǎng)開發(fā)工具 DP83848 MAU CARD IND TEMP RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| DP83848I-POE-EK | 功能描述:以太網(wǎng)開發(fā)工具 DP83848 POE CARD IND TEMP RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
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