參數(shù)資料
型號: DP83848HSQ/NOPB
廠商: National Semiconductor
文件頁數(shù): 16/82頁
文件大?。?/td> 0K
描述: IC TXRX ETHERNET PHYTER 40-LLP
產(chǎn)品培訓(xùn)模塊: PHYTER® Family
標(biāo)準(zhǔn)包裝: 1
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: 以太網(wǎng)
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-LLP-EP(6x6)
包裝: 剪切帶 (CT)
配用: DP83848H-MAU-EK-ND - BOARD EVALUATION DP83848H
其它名稱: *DP83848HSQ/NOPB
DP83848HSQCT
www.national.com
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3.3.3 Serial Management Preamble Suppression
The DP83848H supports a Preamble Suppression mode
as indicated by a one in bit 6 of the Basic Mode Status
Register (BMSR, address 01h.) If the station management
entity (i.e. MAC or other management controller) deter-
mines that all PHYs in the system support Preamble Sup-
pression by returning a one in this bit, then the station
management entity need not generate preamble for each
management transaction.
The DP83848H requires a single initialization sequence of
32 bits of preamble following hardware/software reset. This
requirement is generally met by the mandatory pull-up
resistor on MDIO in conjunction with a continuous MDC, or
the management access made to determine whether Pre-
amble Suppression is supported.
While the DP83848H requires an initial preamble
sequence of 32 bits for management initialization, it does
not require a full 32-bit sequence between each subse-
quent transaction. A minimum of one idle bit between man-
agement transactions is required as specified in the IEEE
802.3u specification.
Figure 4. Typical MDC/MDIO Read Operation
Figure 5. Typical MDC/MDIO Write Operation
MDC
MDIO
00 0
11
110 0 00 000
(STA)
Idle
Start
Opcode
(Read)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
TA
Register Data
Z
MDIO
(PHY)
Z
0 0 0 1 1 0 0 0 1 0 0 0000 0 0 Z
Idle
Z
MDC
MDIO
00
0
11
11 0 0 0 0 000
(STA)
Idle
Start Opcode
(Write)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
TA
Register Data
Z
0 0 0
0 00
0 0 0 0 0 000 Z
Idle
10 0
0
Z
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