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| 型號： | DNC3X3625 |
| 廠商： | Lineage Power |
| 英文描述： | Hex 10/100 Mbits/s Ethernet Transceiver Macrocell(六通道 10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器宏單元) |
| 中文描述： | 六角10/100 Mbits /秒以太網(wǎng)收發(fā)器宏單元（六通道1000萬位/秒和100海里位/秒以太網(wǎng)收發(fā)器宏單元） |
| 文件頁數(shù)： | 31/32頁 |
| 文件大?。?/td> | 464K |
| 代理商： | DNC3X3625 |
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Advance Data Sheet
March 2000
DNC3X3625
10/100 Mbits/s Ethernet Transceiver Macrocell
31
4
Application Notes: Board Layout
Board Layout Considerations
In order to obtain optimum performance, careful atten-
tion must be paid to the circuit board layout, shielding,
and the placement of components. Careful routing of
high-speed lines is mandatory. Power supply input pins
must be protected from noisy conditions by proper fil-
tering. To achieve these design goals, the following
steps are recommended as a minimum.
1. As a minimum, a four-layer circuit board, with two-
ounce copper planes, should be used. This will mini-
mize the switching transients by providing a low-
impedance power source. The signal planes should
be isolated from each other by the power and/or
ground planes. Do not segment the ground plane
except around the RJ-45 connectors and magnetics
module as described below. Use a single, continu-
ous plane. The reference design will be a six-layer
board.
2. Power and ground planes should extend underneath
the ASIC up to the input of the magnetic module.
Power and ground planes should not extend under
any network signal path, or the magnetics module,
because common-mode power supply noise will be
coupled to the signals. The greater the distance
between the planes and the network signals, the
lower the EMI emissions. Chassis ground may be
used under the RJ-45 connectors if desired.
3. The power plane of the ASIC should be separated
into three regions: digital power (V
DDD;
this is the
PWB’s V
DD
plane), analog power (V
DDA
), and output
driver power (V
DDO
). For conservative designs, the
V
DDA
segment and the V
DDO
segment, should be fil-
tered with a ferrite bead, 10
μ
F, and 0.01
μ
F capaci-
tors before connecting to the V
DD
plane with a heavy
wide trace. Pins 80 V
DDPLL
and 83 V
DDPD
can be
connected together and filtered with a ferrite bead
and 10
μ
F and 0.01
μ
F capacitors for conservative
designs. Refer to Figure 3 for suggested layout. Do
not overlay different power planes on different layers,
unless they are separated by a ground plane. When
segmenting power planes on the same layer they
should be separated by at least three times the dis-
tance to the nearest ground layer.
4. The liberal use of capacitors on each the power pins
of the ASIC will minimize any noise coupled into the
power plane. Power supply noise contributes to the
EMI emissions in circuit layouts. Low ESR capacitors
between the power and ground planes must be
placed as close as possible to all the DNC3X3625
power pins. Low-inductance short connections to
each power pin and the ground plane are required.
This can be achieved by using short traces to the
power pins and connecting to the ground plane with
two vias. Multilayer ceramic capacitors with good
quality dielectric such as NPO or X7R (avoid using
Z5U) are recommended for the low ESR capacitors.
A 0.01
μ
F capacitor should be used on every pin, for
conservative designs two capacitors can be used on
every pin a 0.1
μ
F and a 0.001
μ
F.
5. Route the transmit and receive pairs between the
ASIC, the magnetics, and the RJ-45 connectors as
short, straight, and equal length as possible. These
traces should be routed with 50
impedance to the
nearest power/ground plane with a differential
impedance of 100
. Keep the separation between
adjacent pairs on the same layer, 2 mm or more if
possible to minimize crosstalk.
6. The most EMI critical routing is between the mag-
netic module (after common-mode filters) and the
RJ-45 connectors. Use the chassis of the system to
allow coupled noise to flow to ground via common
mode terminations. The chassis is not a perfect
ground, but with proper power supply design, the
chassis can be used to redirect some common-
mode noise.
7. Reduce the number of vias on the transmit path.
Vias can have resonance at critical frequencies
degrading EMI emissions performance. The transmit
differential pairs from the RJ-45 to the magnetics
and the DNC3X3625 can be run on the top layer of
the board. Vias on the receive path should be mini-
mized but are less critical because the signal energy
is less than on the transmit path. The receive signals
can be run on a buried layer or on the bottom layer.
8. Ensure that the 25 MHz crystal and the load capaci-
tors (33 pF), or the oscillator (25 MHz, 50 MHz, or
125 MHz, if used), are located as close to the XLO/
XHI pins as possible. All bias resistors (pins 13, 25,
42, and 43) and reference capacitor (pin 81) must be
located within close proximity to the PHY. This will
reduce the coupled noise into the bias circuits. Place
receive twisted-pair terminating resistors (100
) as
close to PHY pins as possible.
9. Never route clock or high-speed signal lines under
the ASIC unless the lines are under a ground or
power plane.
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