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| 型號： | DNC3X3625 |
| 廠商： | Lineage Power |
| 英文描述： | Hex 10/100 Mbits/s Ethernet Transceiver Macrocell(六通道 10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器宏單元) |
| 中文描述： | 六角10/100 Mbits /秒以太網(wǎng)收發(fā)器宏單元（六通道1000萬位/秒和100海里位/秒以太網(wǎng)收發(fā)器宏單元） |
| 文件頁數(shù)： | 13/32頁 |
| 文件大?。?/td> | 464K |
| 代理商： | DNC3X3625 |
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Advance Data Sheet
March 2000
DNC3X3625
10/100 Mbits/s Ethernet Transceiver Macrocell
13
4
MII Station Management
Basic Operation
The primary function of station management is to transfer control and status information about the DNC3X3625 to
a management entity. This function is accomplished by the MDC clock input, which has a maximum frequency of
25 MHz, along with the MDIO signal.
The MII management interface uses MDC and MDIO to physically transport information between the PHY and the
station management entity.
In the DNC3X3625, the MDIO pin is implemented as three signals: MDIO_IN, MDIO_OUT, and MDIO_HIZ.
MDIO_IN is the information coming from the MAC and is ignored during the TA and DATA fields for MDIO reads.
MDIO_HIZ will be high except during MDIO reads, in which case MDIO_OUT is the PHY data. Under no condition
should the input MDIO_IN be 3-stated. These can be connected to control an I/O buffer if off-chip access is
required.
A specific set of registers and their contents (described in Table 9) defines the nature of the information transferred
across the MDIO interface. Frames transmitted on the MII management interface will have the frame structure
shown in Table 8. The order of bit transmission is from left to right. Note that reading and writing the management
register must be completed without interruption. The port addresses are set by the MGT_ADD pin (see Table 6 for
more detail).
Table 8. MII Management Frame Format
Table 9. MII Management Frames—Field Description
Read/Write
(R/W)
R
W
Pre
ST
OP
PHYAD
REGAD
TA
DATA
IDLE
1 . . . 1
1 . . . 1
01
01
10
01
AAAAA
AAAAA
RRRRR
RRRRR
Z0
10
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
Z
Z
Field
Pre
Descriptions
Preamble
. The DNC3X3625 will accept frames with no preamble. This is indicated by a 1 in
register 1, bit 6.
Start of Frame.
The start of frame is indicated by a 01 pattern.
Operation Code
. The operation code for a read transaction is 10. The operation code for a write
transaction is a 01.
PHY Address
. The PHY address is 5 bits, allowing for 32 unique addresses. The first PHY address
bit transmitted and received is the MSB of the address. A station management entity that is
attached to multiple PHY entities must have prior knowledge of the appropriate PHY address for
each entity.
Register Address.
The register address is 5 bits, allowing for 32 unique registers within each PHY.
The first register address bit transmitted and received is the MSB of the address.
Turnaround
. The turnaround time is a 2-bit time spacing between the register address field, and
the data field of a frame, to avoid drive contention on MDIO during a read transaction. During a
write to the DNC3X3625, these bits are driven to 10 by the station. During a read, the MDIO is not
driven during the first bit time and is driven to a 0 by the DNC3X3625 during the second bit time.
Data
. The data field is 16 bits. The first bit transmitted and received will be bit 15 of the register
being addressed.
Idle Condition.
The IDLE condition on MDIO is a high-impedance state. All three state drivers will
be disabled and the PHY’s pull-up resistor will pull the MDIO line to a logic 1.
ST
OP
PHYADD
REGAD
TA
DATA
IDLE
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