參數(shù)資料
型號(hào)： DNC3X3625
廠商： Lineage Power
英文描述： Hex 10/100 Mbits/s Ethernet Transceiver Macrocell(六通道 10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器宏單元)
中文描述： 六角10/100 Mbits /秒以太網(wǎng)收發(fā)器宏單元（六通道1000萬(wàn)位/秒和100海里位/秒以太網(wǎng)收發(fā)器宏單元）
文件頁(yè)數(shù)： 28/32頁(yè)
文件大小： 464K
代理商： DNC3X3625
28
DNC3X3625
10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet
March 2000
4
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
R = read, LH = latched high.
Table 27. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions
Bit
*
Type
R
Description
28.1 (LNK100UP)
Link Up 100.
This bit, when set to a 1, indicates a 100 Mbits/s transceiver is up
and operational.
Link Up 10.
This bit, when set to a 1, indicates a 10 Mbits/s transceiver is up and
operational.
28.0 (LNK10UP)
R
Bit
*
Type
R/W
Description
29.15 (LOCALRST)
Management Reset.
This is the local management reset bit. Writing a logic 1 to
this bit will cause the lower 16 registers and registers 28 and 29 to be reset to
their default values. This bit is self-clearing.
Generic Reset 1.
This register is used for manufacture test only.
Generic Reset 2.
This register is used for manufacture test only.
100 Mbits/s Transmitter Off.
When this bit is set to 0, it forces TPI low and
TPIB high. This bit defaults to 1.
LED Blinking.
This register, when 1, enables LED blinking. This is ORed with
LED_BLINK_EN. Default is 0.
Carrier Sense Select.
MCRS will be asserted on receive only when this bit is
set to a 1. If this bit is set to logic 0, MCRS will by asserted on receive or trans-
mit. This bit is ORed with the CRS_SEL pin.
Link Error Indication.
When this bit is a 1, a link error code will be reported on
MRXD[3:0] of the DNC3X3625 when MRX_ER is asserted on the MII. The spe-
cific error codes are listed in the MRXD pin description. If it is 0, it will disable this
function.
Packet Error Indication Enable.
When this bit is a 1, a packet error code,
which indicates that the scrambler is not locked, will be reported on MRXD[3:0]
of the DNC3X3625 when MRX_ER is asserted on the MII. When this bit is 0, it
will disable this function.
Pulse Stretching.
When this bit is set to 1, the CS, XS, and RS output signals
will be stretched between approximately 42 ms—84 ms. If this bit is 0, it will dis-
able this feature. Default state is 0.
Encoder/Decoder Bypass.
When this bit is set to 1, the 4B/5B encoder and
5B/4B decoder function will be disabled. This bit is ORed with the EDBT pin.
Symbol Aligner Bypass.
When this bit is set to 1, the aligner function will be
disabled.
Scrambler/Descrambler Bypass.
When this bit is set to 1, the scrambling/
descrambling functions will be disabled. This bit is ORed with the SDBT pin.
Carrier Integrity Enable.
When this bit is set to a 1, carrier integrity is enabled.
This bit is ORed with the CARIN_EN pin.
Jam Enable.
When this bit is a 1, it enables JAM associated with carrier integrity
to be ORed with MCOLMCRS.
29.14 (RST1)
29.13 (RST2)
29.12 (100_OFF)
R/W
R/W
R/W
29.11 (LED_BLINK
R/W
29.10 (CRS_SEL)
R/W
29.9 (LINK_ERR)
R/W
29.8 (PKT_ERR)
R/W
29.7 (PULSE_STR)
R/W
29.6 (EDB)
R/W
29.5 (SAB)
R/W
29.4 (SDB)
R/W
29.3 (CARIN_EN)
R/W
29.2 (JAM_COL)
R/W
Register Information
(continued)
Table 26. MR28—Device-Specific Register 1 (Status Register) Bit Descriptions
(continued)
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
R = read, W = write.
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