參數(shù)資料
型號： DNC3X3625
廠商： Lineage Power
英文描述： Hex 10/100 Mbits/s Ethernet Transceiver Macrocell(六通道 10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器宏單元)
中文描述： 六角10/100 Mbits /秒以太網(wǎng)收發(fā)器宏單元（六通道1000萬位/秒和100海里位/秒以太網(wǎng)收發(fā)器宏單元）
文件頁數(shù)： 2/32頁
文件大?。?/td> 464K
代理商： DNC3X3625
DNC3X3625
10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet
March 2000
2
Table of Contents
Contents
Page
Features ....................................................................................................................................................................1
Hex 10 Mbits/s Transceiver .....................................................................................................................................1
Hex 100 Mbits/s Transceiver...................................................................................................................................1
Hex 100 Mbits/s FX Transceiver..............................................................................................................................1
General ...................................................................................................................................................................1
Description ................................................................................................................................................................4
Functional Block Diagram .......................................................................................................................................4
Macrocell I/Os.........................................................................................................................................................5
Signal Information......................................................................................................................................................6
Signal Descriptions.................................................................................................................................................6
MII Station Management .........................................................................................................................................13
Basic Operation ....................................................................................................................................................13
MII Interface Design ................................................................................................................................................14
Absolute Maximum Ratings.....................................................................................................................................14
Electrical Characteristics.........................................................................................................................................15
Register Information................................................................................................................................................19
Register Descriptions............................................................................................................................................19
Application Notes: Board Layout .............................................................................................................................31
Board Layout Considerations................................................................................................................................31
Tables
Page
Table 1. MII/5-Bit Serial Interface Signals.................................................................................................................6
Table 2. MII Management Signals ............................................................................................................................7
Table 3. 10/100 Mbits/s Twisted-Pair (TP) Interface Signals.....................................................................................7
Table 4. Status Signals.............................................................................................................................................8
Table 5. Clock and Reset Signals.............................................................................................................................9
Table 6. Control/Status Signals ..............................................................................................................................10
Table 7. Testability Signals......................................................................................................................................12
Table 8. MII Management Frame Format................................................................................................................13
Table 9. MII Management Frames—Field Description............................................................................................13
Table 10 . Absolute Maximum Ratings ...................................................................................................................14
Table 11 . Operating Conditions .............................................................................................................................14
Table 12. Summary of Management Registers (MR) .............................................................................................19
Table 13. MR0—Control Register Bit Descriptions.................................................................................................20
Table 14. MR1—Status Register Bit Descriptions ..................................................................................................21
Table 15. MR2, MR3—PHY Identification Registers (1 and 2) Bit Descriptions.....................................................22
Table 16. MR4—Autonegotiation Advertisement Register Bit Descriptions............................................................22
Table 17. MR5—Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions................................23
Table 18. MR5—Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Descriptions.........................23
Table 19. MR6—Autonegotiation Expansion Register Bit Descriptions..................................................................24
Table 20. MR7—Next Page Transmit Register Bit Descriptions..............................................................................25
Table 21. MR16—PCS Control Register Bit Descriptions.......................................................................................25
Table 22. MR17—Autonegotiation Read Register A...............................................................................................26
Table 23. MR18—Autonegotiation Read Register B...............................................................................................26
Table 24. MR20—User-Defined Register ...............................................................................................................27
Table 25. MR21—RXER Counter...........................................................................................................................27
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