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參數(shù)資料
| 型號： | DDX4100ERRATA |
| 英文描述： | DDX4100 Errata January 17 2002 |
| 中文描述： | DDX4100勘誤表02年1月17日 |
| 文件頁數(shù)： | 25/27頁 |
| 文件大?。?/td> | 1737K |
| 代理商： | DDX4100ERRATA |
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DDX-4100
12.11 Phantom Center Register (address 60h) (AC’97 only)
D15 D14 D13 D12 D11 D10
Setting bit D0=1 enables the Phantom Center Channel in AC’97 operation. When enabled, the content of
the center channel is split and added to the L and R channels. Default setting is 0h.
12.12 Static EQ and Side Firing Register (address 70h)
D15 D14 D13 D12 D11 D10
D9
D8
D7
This register controls the activation of the Static EQ and the Side Firing surround sound.
EQ1
EQ0
Result
0
0
EQ off (default)
0
1
EQ enabled
1
x
Side Firing + EQ
For more information on setting EQ parameters, see Paragraph 9.2
12.13 Bass Management Register (address 72h)
D15 D14 D13
D11 D10
D9
D8
D7
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Phantom
D6
D5
D4
D3
D2
D1
EQ1 EQ0
D0
D6
D5
D4
D3
D2
D1
D0
Bass
Mng
D12
Setting bit D0=1 activates the Bass Management. For more information on Bass Management, See
Paragraph 9.1. Default setting is 0h.
12.14 Bypass Register (address 74h)
D15 D14 D13 D12 D11 D10
D9
D8
Setting bit D0=1 bypasses the DSP block. All channels are bypassed and output equal to input,
regardless of all other algorithm register settings (Volume, Tone, Phantom, EQ). Default is 0h.
12.15 BIST and Status Register (BASR): (address 76h)
D15
D14
D13
D12
D11
D10
D9
D8
DSP_
BIST_
START
RUNNIN
G
D7
D6
D5
D4
D3
D2
D1
D0
Bypass
D7
DDX_
DPRAM
D6
DDX_
SPRAM
_3
D5
DDX_
SPRAM
_2
D4
DDX_
SPRAM
_1
D3
BIST
_STOP
D2
BIST
_START
D1
SPDIF_
STATUS
D0
SRC_
STATUS
DSP_
BIST_
DSP_
BIST_
STOP
DSP_
RAM
X
X
SRC_
SPRAM
_2
SRC_
SPRAM
_1
25
Details and Specifications are subject to change without notice
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