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參數(shù)資料
| 型號： | DDX4100ERRATA |
| 英文描述： | DDX4100 Errata January 17 2002 |
| 中文描述： | DDX4100勘誤表02年1月17日 |
| 文件頁數(shù)： | 2/27頁 |
| 文件大?。?/td> | 1737K |
| 代理商： | DDX4100ERRATA |
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DDX-4100
GENERAL DESCRIPTION
(continued)
In the IIS/SPDIF mode, a stereo S/PDIF and a 4 channel three-wire programmable serial input interface
support any sampling frequency in the continuous range from 32 to 96 KHz. The programmable serial
interface supports up to four channels including the standard IIS protocol. Operation of the S/PDIF or the
IIS inputs is mutually exclusive.
An embedded high quality sample rate converter (SRC) re-samples input data at the internal fixed
sampling frequency of 48 kHz for DSP operations. The DSP is a 20 x 20 bit core audio processor
performing several user controlled parametric algorithms, among them are static equalization, Bass,
Treble, Volume control and more. The DSP operates at 49.152MHz (1024xfs). This frequency is
generated by an internal PLL with programmable multiplication factor (x2 or x8) in conjunction with the
built-in oscillator or an external clock input.
The device includes 5 channels of Direct Digital Amplification (DDX), providing PWM output signals
used to directly drive external high efficiency class-D power bridge stages (DDX-2060). Additionally, a
programmable 6-channel digital output interface (supporting IIS standard protocol) is embedded for
applications with standard audio D/A converters. The output sampling frequency is fixed at 48 kHz when
the interface operates as a master. An over-sampling clock (256xfs or 512xfs) is provided for external
D/A converters.
An IIC interface allows programming of internal algorithms and control registers via an external controller.
Arbitration logic handles access conflicts to embedded control registers (which may occur as a
consequence of simultaneous access to control registers by Aclink, IIC and DSP blocks).
PIN CONNECTION (Top View)
1
2
3
5
6
4
7
8
9
10
17
11
18
19
20
21
22
44
43
42
41
39
40
38
37
36
35
34
28
27
26
24
23
25
33
32
31
29
30
SDI_1/SDATA_OUT
SDI_2/SDATA_IN
LRCKI/SYNC
BICKI/BIT_CLK
VDD_1
GND_1
RESET
AC97_MODE
SDA
SCL
SA
T
V
X
X
G
V
R
R
V
L
L
S
E
L
S
S
S
S
G
V
C
P
SRIGHT_B
SRIGHT_A
GND_3
VDD_3
RIGHT_B
RIGHT_A
LEFT_B
LEFT_A
GND_4
VDD_4
SLEFT_B
12
13
14
15
16
2
Details and Specifications are subject to change without notice
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