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參數(shù)資料
| 型號： | DDX4100ERRATA |
| 英文描述： | DDX4100 Errata January 17 2002 |
| 中文描述： | DDX4100勘誤表02年1月17日 |
| 文件頁數(shù)： | 11/27頁 |
| 文件大?。?/td> | 1737K |
| 代理商： | DDX4100ERRATA |
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DDX-4100
PR5 bit (reg. 26h, bit D13) – Setting this bit will cause a partial power down of the device, with all
the clocks suspended except those that are required to keep the AC97 and I
C cells alive. In this
way, using either of these input interfaces makes it possible to resume from this state simply by
resetting the PR5 bit.
EAPD bit (reg. 26h, bit D15) – The External Amplifier Power Down bit controls the state of the
related pin (EAPD), which in turn, is used to switch off the external power device.
Figure 6:
Power Down Management
LR: Reg 02h bit 15
LFE: reg 36h bit 15
SR: reg 39h bit 07
SL: reg 38h bit 15
Internal CK
Disable
Chip
powerdown
EAPD pin
(active LOW)
SR
SL
LR
LFE
reg 26h, bit 15
reg 7EFh, bit 0
DSP
Requests
EAPD
PWDN
reg 26h, bit 13
PR5
To avoid any extraneous noise while switching between the various powerdown modes, a masking
technique has been adopted to drive the actual controlling signals. As shown in Figure 3 a powerdown
request will instruct the DSP to perform a volume fade-out and MUTE of all channels. The external power
device will also be turned off (via the EAPD pin) not only as a consequence of an EAPD request, but also
as a consequence of a PR5 or PWDN request, preventing any possible noise.
9.0
BASS MANAGEMENT AND EQ
The DDX-4100 has the ability to redirect sound to the SBW,(subwoofer), channel and to pass each
channel through a 4 stage cascaded 2
nd
order IIR filter. With the combination of the DDX
gain/compressor (CRA register bits 2-3) a dynamic EQ can be implemented. Additionally, a special Side-
Firing sound can be achieved by enabling this feature available with the ready-made filter topology on the
surround channels.
11
Details and Specifications are subject to change without notice
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