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參數(shù)資料
| 型號： | DDX4100ERRATA |
| 英文描述： | DDX4100 Errata January 17 2002 |
| 中文描述： | DDX4100勘誤表02年1月17日 |
| 文件頁數(shù)： | 13/27頁 |
| 文件大?。?/td> | 1737K |
| 代理商： | DDX4100ERRATA |
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DDX-4100
9.3 Surround Side Firing
Instead of the normal filters described in the previous section above, a special topology is available for
the surround channels:
Figure 9: Side Firing connections for Surround channels
By designing appropriate filters, special surround sound can be achieved where surround speakers are
located next to the front speakers and rotated to the sides. By setting Static EQ and Side Firing (address
70h, section 12.11), this Side Firing topology is enabled.
10.0 EQ AND BASS MANAGEMENT COEFFICIENT HANDLING
In order to implement the Static EQ filters and the Bass management, a RAM space for user coefficients
has been included in this device. Beginning with address 240h (YRAM), there are 69 x 20 bit registers
available for this purpose. To read or write into these registers the application software must follow an
indirect addressing approach. As shown in Figure 8, there are two AC’97 dedicated registers, (4 x 8 bit
registers for I
C addressing), to access the coefficient table. In register 78h (78h + 79h in I
C addressing)
the 16 low bits of the coefficient are stored either by the user for a write operation, or by the internal logic
for a read operation. The upper 4 bits are stored in the lowest nibble of register 7Ah (7Bh in I
2
C
addressing). The address of the coefficient on which the R/W operation must be performed is stored in
the high byte of register 7Ah. The address is derived by adding the coefficient index to the base location
40h.
To select between Read or Write operation the ‘R’ bit in register 7Ah (7Bh in I
2
C addressing) must be
properly setup. The actual read/write operation will start after register 7Ah (7Bh in I
2
C addressing) has
been written. The following explains this in more detail:
Coefficient registers usage
Bit
15
AC’97
I2C
Figure 6
Right Surround
Input
Right Surround
Output
Left Surround
Output
Left Surround
Input
+
+
and
Phase
Inverting
bi-
quad
bi-
quad
Scale
in
bi-
quad
bi-
quad
bi-
quad
bi-
quad
bi-
quad
bi-
quad
Scale
in
Bit
0
7Ah
Coefficient (19..16)
R-x-x-x
Coeff. Address (8 bits)
Coefficient (15..0)
7Bh
79h
7Ah
78h
78h
R: set this bit to 1 for reading, 0 for writing a coefficient.
13
Details and Specifications are subject to change without notice
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