參數(shù)資料
型號: DC798B
廠商: Linear Technology
文件頁數(shù): 24/42頁
文件大?。?/td> 0K
描述: BOARD DELTA SIGMA ADC LTC2480
軟件下載: QuikEval System
設(shè)計資源: DC798B Design File
DC798B Schematic
標準包裝: 1
系列: QuikEval™
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 7.5
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
已用 IC / 零件: LTC2480
已供物品:
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LTC2480
0
2480fd
applicaTions inForMaTion
voltage). Table 7 summarizes the effects of mismatched
source impedance and differences in reference/input
common mode voltages.
Table 7. Suggested Input Configuration for LTC2480
BALANCED INPUT
RESISTANCES
UNBALANCED INPUT
RESISTANCES
Constant
VIN(CM) – VREF(CM)
CEXT > 1nF at Both
IN+ and IN. Can Take
Large Source Resistance
with Negligible Error
CEXT > 1nF at Both IN+
and IN. Can Take Large
Source Resistance.
Unbalanced Resistance
Results in an Offset
Varying
VIN(CM) – VREF(CM)
CEXT > 1nF at Both IN+
and IN. Can Take Large
Source Resistance with
Negligible Error
Minimize IN+ and IN
Capacitors and Avoid
Large Source Impedance
(<5kΩ Recommended)
Themagnitudeofthedynamicinputcurrentdependsupon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
andpowersupplyrangeistypicallybetterthan0.5%.Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and
IN, the expected drift of the dynamic current and offset
will be insignificant (about 1% of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 1k source resistance will create a
1V typical and 10V maximum offset voltage.
Reference Current
In a similar fashion, the LTC2480 samples the differential
reference pins VREF+ and GND transferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can
be analyzed in two distinct situations.
For relatively small values of the external reference capaci-
tors (CREF < 1nF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 1nF) may be
requiredasreferencefiltersincertainconfigurations.Such
capacitors will average the reference sampling charge and
the external source resistance will see a quasi constant
reference differential impedance.
In the following discussion, it is assumed the input and
reference common mode are the same. Using internal
oscillator for 60Hz mode, the typical differential reference
resistance is 1MΩ which generates a full-scale (VREF/2)
gain error of 0.51ppm for each ohm of source resistance
driving the VREF pin. For 50Hz/60Hz mode, the related
difference resistance is 1.1MΩ and the resulting full-scale
error is 0.46ppm for each ohm of source resistance driv-
ing the VREF pin. For 50Hz mode, the related difference
resistance is 1.2MΩ and the resulting full-scale error is
0.42ppm for each ohm of source resistance driving the
VREF pin. When fO is driven by an external oscillator with a
frequency fEOSC(externalconversionclockoperation),the
typicaldifferentialreferenceresistanceis0.301012/fEOSC
Ω and each ohm of source resistance driving the VREF pin
will result in 1.67 10–6 fEOSCppm gain error. The typical
+FS and –FS errors for various combinations of source
resistance seen by the VREF pin and external capacitance
connected to that pin are shown in Figures 15-18.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
The INL is caused by the input dependent terms
–VIN2/(VREF REQ) – (0.5 VREF DT)/REQ in the reference
pin current as expressed in Figure 11. When using internal
oscillator and 60Hz mode, every 100Ω of reference source
resistance translates into about 0.67ppm additional INL
error.Whenusinginternaloscillatorand50Hz/60Hzmode,
every 100Ω of reference source resistance translates into
about 0.61ppm additional INL error. When using internal
oscillator and 50Hz mode, every 100Ω of reference source
resistance translates into about 0.56ppm additional INL
error. When fO is driven by an external oscillator with a
frequency fEOSC, every 100Ω of source resistance driving
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