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參數資料
| 型號： | DC798B |
| 廠商： | Linear Technology |
| 文件頁數： | 20/42頁 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2480 |
| 軟件下載： | QuikEval System |
| 設計資源： | DC798B Design File DC798B Schematic |
| 標準包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數量： | 1 |
| 位數： | 16 |
| 采樣率（每秒）： | 7.5 |
| 數據接口： | MICROWIRE?，串行，SPI? |
| 已用 IC / 零件： | LTC2480 |
| 已供物品： | 板 |
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LTC2480
2480fd
Digital Signal Levels
The LTC2480’s digital interface is easy to use. Its digital
inputs (SDI, fO, CS and SCK in External SCK mode of
operation) accept standard CMOS logic levels and the
internal hysteresis receivers can tolerate edge transition
times as slow as 100s. However, some considerations
are required to take advantage of the exceptional accuracy
and low supply current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(VCC – 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (SDI, fO, CS and
SCKinExternalSCKmodeofoperation)iswithinthisrange,
the power supply current may increase even if the signal in
questionisatavalidlogiclevel.Formicropoweroperation,
it is recommended to drive all digital input signals to full
CMOS levels [VIL < 0.4V and VOH > (VCC – 0.4V)].
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the pins can
severely disturb the analog to digital conversion process.
Undershoot and overshoot occur because of the imped-
ance mismatch of the circuit board trace at the converter
pin when the transition time of an external control signal
is less than twice the propagation delay from the driver
to the LTC2480. For reference, on a regular FR-4 board,
signal propagation velocity is approximately 183ps/inch
for internal traces and 170ps/inch for surface traces.
Thus, a driver generating a control signal with a minimum
transition time of 1ns must be connected to the converter
pin through a trace shorter than 2.5 inches. This problem
becomesparticularlydifficultwhensharedcontrollinesare
used and multiple reflections may occur. The solution is
to carefully terminate all transmission lines close to their
characteristic impedance.
Parallel termination near the LTC2480 pin will eliminate
this problem but will increase the driver power dissipa-
tion. A series resistor between 27Ω and 56Ω placed near
the driver output pin will also eliminate this problem
without additional power dissipation. The actual resistor
value depends upon the trace impedance and connection
topology.
Analternatesolutionistoreducetheedgerateofthecontrol
signals. It should be noted that using very slow edges will
increase the converter power supply current during the
transition time. The differential input architecture reduces
the converter’s sensitivity to ground currents.
Particular attention must be given to the connection of
the fO signal when the LTC2480 is used with an external
conversion clock. This clock is active during the conver-
sion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals can result in DC gain and INL errors.
A normal mode signal of this frequency at the converter
input terminals can result in a DC offset error. Such pertur-
bations can occur due to asymmetric capacitive coupling
between the fO signal trace and the converter input and/or
reference connection traces. An immediate solution is to
maintain maximum possible separation between the fO
signal trace and the input/reference signals. When the fO
signal is parallel terminated near the converter, substantial
AC current is flowing in the loop formed by the fO con-
nection trace, the termination and the ground return path.
Thus,perturbationsignalsmaybeinductivelycoupledinto
the converter input and/or reference. In this situation, the
user must reduce to a minimum the loop area for the fO
signal as well as the loop area for the differential input
and reference connections. Even when fO is not driven,
other nearby signals pose similar EMI threats which will
be minimized by following good layout practices.
applicaTions inForMaTion
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