參數(shù)資料
型號(hào): DAC1627D1G25HN
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 16-bit DAC, up to 1.25 Gsps; 2x 4x and 8x interpolating
封裝: DAC1627D1G25HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;
文件頁(yè)數(shù): 68/69頁(yè)
文件大小: 1677K
代理商: DAC1627D1G25HN
DAC1627D1G25
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 29 April 2011
68 of 69
NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 70. DAC_CURRENT_2 register (address 11h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 71. DAC_CURRENT_3 register (address 12h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 72. DAC_CURRENT_4 register (address 13h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 73. DAC_CURRENT_5 register (address 14h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 74. DAC_CURRENT_6 register (address 15h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 75. Bias current control table . . . . . . . . . . . . . . . . .52
Table 76. DAC_PON_SLEEP register (address 16h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 77. DAC_TEST_8 register (address 17h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 78. SPI_PAGE register (address 1Fh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 79. Page_0A register allocation map . . . . . . . . . . .54
Table 80. Register MAIN_CNTRL (address 00h) . . . . . .56
Table 81. Register MAN_LDCLKDEL (address 01h) . . . .56
Table 82. Register DBG_LVDS (address 02h) . . . . . . . .56
Table 83. Register RST_EXT_LCLK (address 04h) . . . .56
Table 84. Register RST_EXT_DCLK (address 05h) . . . .57
Table 85. Register DCSMU_PREDIV (address 06h) . . . .57
Table 86. Register LD_POL_LSB (address 08h) . . . . . . .57
Table 87. Register LD_POL_MSB (address 09h) . . . . . .57
Table 88. Register LD_CNTRL (address 0Ah) . . . . . . . .57
Table 89. Register MISC_CNTRL (address 0Bh) . . . . . .58
Table 90. Register I_DC_LVL_LSB(address 0Ch) . . . . .59
Table 91. Register I_DC_LVL_MSB(address 0Dh) . . . . .59
Table 92. Register Q_DC_LVL_LSB(address 0Eh) . . . . .59
Table 93. Register Q_DC_LVL_MSB(address 0Fh) . . . .59
Table 94. Register TYPE_ID (address 1Bh) . . . . . . . . . .59
Table 95. Register DAC_VERSION (address 1Ch) . . . . .60
Table 96. Register DIG_VERSION (address 1Dh) . . . . .60
Table 97. Register DIG_VERSION (address 1Eh) . . . . .60
Table 98. Register PAGE_ADD (address 1Fh) . . . . . . . .60
Table 99. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 100. Revision history . . . . . . . . . . . . . . . . . . . . . . . .64
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