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| 型號(hào)： | DAC1627D1G25HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC, up to 1.25 Gsps; 2x 4x and 8x interpolating |
| 封裝： | DAC1627D1G25HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,; |
| 文件頁數(shù)： | 22/69頁 |
| 文件大?。?/td> | 1677K |
| 代理商： | DAC1627D1G25HN |
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DAC1627D1G25
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 29 April 2011
22 of 69
NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
10.7.1
CDI mode 0 (x2 interpolation)
CDI mode 0 (
×
2 interpolation) is required when the value of the LVDS DDR clock is twice
the internal maximum CDI frequency.
Table 12
shows examples of applications using an
internal PLL or an external clock for the DAC core.
[1]
Bits CDI_MODE[1:0] of register MISC_CNTRL (see
Table 89
).
[2]
Bits INTERPOLATION[1:0] of register TXCFG (see
Table 25
).
[3]
If a Single Sideband Modulator (SSBM) is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see
Table 25
).
[4]
Pins CLKP and CLKN (see
Figure 2
).
[5]
Bit PLL_PD of register PLLCFG (see
Table 26
).
[6]
Bits PLL_DIV[1:0] of register PLLCFG (see
Table 26
).
10.7.2
CDI mode 1 (x4 interpolation)
CDI mode 1 (
×
4 interpolation) is required when the values of the LVDS DDR clock and the
internal CDI frequency are equal.
Table 13
shows examples of applications using an
internal PLL or an external clock for the DAC core.
[1]
Bits CDI_MODE[1:0] of register MISC_CNTRL (see
Table 89
).
[2]
Bits INTERPOLATION[1:0] of register TXCFG (see
Table 25
).
[3]
If SSBM is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see
Table 25
).
[4]
Pins CLKP and CLKN (see
Figure 2
).
[5]
Bit PLL_PD of register PLLCFG (see
Table 26
).
[6]
Bits PLL_DIV[1:0] of register PLLCFG (see
Table 26
).
Table 12.
LVDS DDR
rate (MHz)
CDI mode 0: operating modes examples
I rate;
Q rate
(Msps)
CDI
mode
[1]
FIR mode
[2]
SSBM
rate
[3]
(Msps)
DAC rate
(Msps)
PLL configuration
PLL
status
[5]
DAC input
clock
[4]
(MHz)
320
640
PLL
divider
[6]
320
320
320
320
0
0
×
2
×
2
640
640
640
640
enabled
disabled
2
n.a.
Table 13.
LVDS DDR
rate (MHz)
CDI mode 1: operating modes examples
I rate;
Q rate
(Msps)
CDI
mode
[1]
FIR mode
[2]
SSBM
rate
[3]
(Msps)
DAC rate
(Msps)
PLL configuration
PLL
status
[5]
DAC input
clock
[4]
(MHz)
250
1000
PLL
divider
[6]
250
250
250
250
1
1
×
4
×
4
1000
1000
1000
1000
enabled
disabled
4
n.a.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC1627D1G25HN/C1, | 功能描述:調(diào)節(jié)器/解調(diào)器 DUAL 16b 1.25GSPS to 1.25 Gsps RoHS:否 制造商:Texas Instruments 封裝 / 箱體:PVQFN-N24 封裝:Reel |
| DAC1627D1G25HN/C1,551 | 功能描述:調(diào)節(jié)器/解調(diào)器 Dual 16-bit DAC, up to 1.25 Gsps RoHS:否 制造商:Texas Instruments 封裝 / 箱體:PVQFN-N24 封裝:Reel |
| DAC1627D1G25HN-C1 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC1627D1G25HN-C18 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN72 - Tape and Reel |
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