參數(shù)資料
型號: DAC1627D1G25HN
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 16-bit DAC, up to 1.25 Gsps; 2x 4x and 8x interpolating
封裝: DAC1627D1G25HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;
文件頁數(shù): 23/69頁
文件大小: 1677K
代理商: DAC1627D1G25HN
DAC1627D1G25
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 29 April 2011
23 of 69
NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
10.7.3
CDI mode 2 (x8 interpolation)
CDI mode 2 (
×
8 interpolation) is required when the LVDS DDR clock is half the maximum
CDI frequency or less.
Table 14
shows examples of applications using an internal PLL or
an external clock for the DAC core.
[1]
Bits CDI_MODE[1:0] of register MISC_CNTRL (see
Table 89
).
[2]
Bits INTERPOLATION[1:0] of register TXCFG (see
Table 25
).
[3]
If SSBM is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see
Table 25
).
[4]
Pins CLKP and CLKN (see
Figure 2
).
[5]
Bit PLL_PD of register PLLCFG (see
Table 26
).
[6]
Bits PLL_DIV[1:0] of register PLLCFG (see
Table 26
).
10.8 FIR filters
The DAC1627D1G25 integrates three selectable Finite Impulse Response (FIR) filters
which enable the use of the device with
×
2,
×
4 or
×
8 interpolation rates. All three
interpolation FIR filters have a stop-band
attenuation of at least 80 dBc and a pass-band
ripple of less than 0.0005 dB.
Table 15
shows the coefficients of the interpolation filters.
Table 14.
LVDS DDR
rate (MHz)
CDI mode 2: operating modes examples
I rate;
Q rate
(Msps)
CDI
mode
[1]
FIR mode
[2]
SSBM
rate
[3]
(Msps)
DAC rate
(Msps)
PLL configuration
PLL
status
[5]
DAC input
clock
[4]
(MHz)
125
1000
PLL
divider
[6]
125
125
125
125
2
2
×
8
×
8
1000
1000
1000
1000
enabled
disabled
4
n.a.
Fig 16. First stage half-band filter response
NF (fs)
0
0.5
0.4
0.2
0.3
0.1
001aao039
magnitude
(dB)
0
-100
-20
-40
-80
-60
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