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參數(shù)資料
| 型號(hào)： | CY8CLED16P01-28PVXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28 |
| 封裝： | 0.210 INCH, LEAD FREE, SSOP-28 |
| 文件頁數(shù)： | 34/58頁 |
| 文件大?。?/td> | 837K |
| 代理商： | CY8CLED16P01-28PVXI |
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CY8CLED16P01
Document Number: 001-49263 Rev. *J
Page 4 of 58
2.2.3 Coupling Circuit Reference Design
The coupling circuit couples low voltage signals from the
CY8CLED16P01 to the powerline. The topology of this circuit is
determined by the voltage on the powerline and design
constraints mandated by powerline usage regulations.
Cypress provides reference designs for a range of powerline
voltages including 110V/240V AC and 12V/24V AC/DC. The
CY8CLED16P01 is capable of data communication over other
AC/DC Powerlines as well with the appropriate external coupling
circuit. The 110V AC and 240V AC designs are compliant to the
following powerline usage regulations:
■ FCC Part 15 for North America
■ EN 50065-1:2001 for Europe
2.3 Network Protocol
Cypress’s powerline optimized network protocol performs the
functions of the data link, network, and transport layers in an
ISO/OSI-equivalent model.
Figure 2-3. Powerline Network Protocol
The network protocol implemented on the CY8CLED16P01
supports the following features:
■ Bidirectional half duplex communication
■ Master-slave or peer-to-peer network topologies
■ Multiple masters on powerline network
■ 8-bit logical addressing supports up to 256 powerline nodes
■ 16-bit extended logical addressing supports up to 65536
powerline nodes
■ 64-bit physical addressing supports up to 2
64 powerline nodes
■ Individual, broadcast or group mode addressing
■ Carrier Sense Multiple Access (CSMA)
■ Full control over transmission parameters
Acknowledged
Unacknowledged
Repeated Transmit
2.3.1 CSMA and Timing Parameters
■ CSMA – The protocol provides the random selection of a period
between 85 and 115 ms (out of seven possible values in this
range). Within this period, the Band-In-Use (BIU) detector must
indicate that the line is not in use, before attempting a trans-
mission.
■ BIU – A Band-In-Use detector, as defined under CENELEC EN
50065-1, is active whenever a signal that exceeds 86 dB
Vrms
anywhere in the range 131.5 kHz to 133.5 kHz is present for
at least 4 ms. This threshold can be configured for different
end-system applications not requiring CENELEC
compliance.The modem tries to retransmit after every 85 to
115 ms when the band is in use. The transmitter times out after
1.1 seconds to 3 seconds (depending on the noise on the
Powerline) and generates an interrupt to indicate that the trans-
mitter was unable to acquire the powerline.
2.3.2 Powerline Transceiver Packet
The powerline network protocol defines a Powerline Transceiver
(PLT) packet structure, which is used for data transfers between
nodes across the powerline. Packet formation and data trans-
mission across the powerline network is implemented internally
in the CY8CLED16P01.
A PLT packet is divided into a variable length header (minimum
6 bytes to maximum 20 bytes, depending on address type),
variable length payload (minimum 0 bytes to maximum 31
bytes), and a packet CRC byte.
This packet (preceded by a one byte preamble "0xAB") is then
transmitted by the powerline modem PHY and the external
coupling circuit across the powerline.
The format of the PLT packet is shown in the following table.
CY
8CL
E
D1
6P
01
Powerline
Network Protocol
Physical Layer
FSK Modem
Powerline Communication Solution
Powerline Transceiver Packet
Programmable
System Resources
Digital and Analog
Peripherals
PSoC Core
Additional System
Resources
MAC, Decimator, I2C,
SPI, UART etc.
PLC Core
Embedded Application
Modulation
Technology
PrISM, PWM etc.
Additional
Communication
Interface
DALI, DMX512
HB LED
Controller
Table 2-1. Powerline Transceiver (PLT) Packet Structure
Byte
Offset
Bit Offset
76
5
4
3
2
1
0
0x00
SA
Type
DA Type Service
Type
RSVD RSVD Response RSVD
0x01
Destination Address
(8-Bit Logical, 16-Bit Extended Logical or 64-Bit Physical)
0x02
Source Address
(8-Bit Logical, 16-Bit Extended Logical or 64-Bit Physical)
0x03
Command
0x04
RSVD
Payload Length
0x05
Seq Num
Powerline Packet Header CRC
0x06
Payload (0 to 31 Bytes)
Powerline Transceiver Packet CRC
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