參數(shù)資料
型號(hào)： CY8CLED16P01-28PVXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28
封裝： 0.210 INCH, LEAD FREE, SSOP-28
文件頁(yè)數(shù)： 29/58頁(yè)
文件大?。?/td> 837K
代理商： CY8CLED16P01-28PVXI
CY8CLED16P01
Document Number: 001-49263 Rev. *J
Page 35 of 58
10.4 AC Electrical Characteristics
10.4.1 AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C
T
A 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Note
See the individual user module data sheets for information on maximum frequencies for user modules.
Table 10-13. AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FIMO24
Internal Main Oscillator Frequency for 24 MHz
23.4
24
24.6
MHz
Trimmed for 5V operation
using factory trim values.
SLIMO Mode = 0.
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.5
6
6.5[6]
MHz
Trimmed for 5V operation
using factory trim values.
SLIMO Mode = 1.
FCPU1
CPU Frequency (5V Nominal)
0.0914
24
24.6[6]
MHz
SLIMO Mode = 0.
F48M
Digital PSoC Block Frequency
0
48
49.2[6, 7]
MHz
Refer to the AC Digital Block
Specifications below.
F32K1
Internal Low Speed Oscillator Frequency
15
32
64
kHz
F32K2
External Crystal Oscillator
–
32.768
–
kHz
Accuracy is capacitor and
crystal dependent. 50% duty
cycle.
F32K_U
Internal Low Speed Oscillator (ILO)
Untrimmed Frequency
5
–
100
kHz
After a reset and before the
m8c starts to run, the ILO is
not trimmed. See the System
Resets section of the PSoC
Technical Reference Manual
for details on timing this.
FPLL
PLL Frequency
–
23.986
–
MHz
A multiple (x732) of crystal
frequency.
TPLLSLEW
PLL Lock Time
0.5
–
10
ms
TPLLSLEWLOW PLL Lock Time for Low Gain Setting
0.5
–
50
ms
TOS
External Crystal Oscillator Startup to 1%
–
250
500
ms
TOSACC
External Crystal Oscillator Startup to 100 ppm
–
300
600
ms
The crystal oscillator
frequency is within 100 ppm
of its final value by the end of
the TOSACC period. Correct
operation assumes a
properly loaded 1
W
maximum drive level 32.768
kHz crystal. -40°C
T
A
85°C.
TXRST
External Reset Pulse Width
10
–
s
SRPOWER_UP Power Supply Slew Rate
–
250
V/ms
Vdd slew rate during power
up.
TPOWERUP
Time from End of POR to CPU Executing Code
–
16
100
ms
Power up from 0V. See the
System Resets section of the
PSoC Technical Reference
Manual
.
DC24M
24 MHz Duty Cycle
40
50
60
%
Notes
temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
6. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
7. See the individual user module data sheets for information on maximum frequencies for user modules.
8. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
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