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參數(shù)資料
| 型號(hào)： | CY8CLED16P01-28PVXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28 |
| 封裝： | 0.210 INCH, LEAD FREE, SSOP-28 |
| 文件頁(yè)數(shù)： | 10/58頁(yè) |
| 文件大?。?/td> | 837K |
| 代理商： | CY8CLED16P01-28PVXI |
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CY8CLED16P01
Document Number: 001-49263 Rev. *J
Page 18 of 58
8. Pin Information
The CY8CLED16P01 PLC device is available in a variety of packages which are listed and illustrated in the following tables. Every
port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.
8.1 28-Pin Part Pinout
Notes
1. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Technical Reference Manual for details.
2. When using the PLT user module, the external crystal is always required for protocol timing. For the FSK modem, either the PLL Mode should be enabled or the
external 24MHz on P1[4] should be selected. The IMO should not be used.
Table 8-1. 28-Pin Part Pinout (SSOP)
Pin
No.
Type
Pin Name
Description
Figure 8-1. CY8CLED16P01 28-Pin PLC Device
Digital
Analog
1
I/O
I
P0[7]
Analog Column Mux Input
2
Reserved
RSVD
Reserved
3
O
FSK_OUT
Analog FSK Output
4
I/O
I
P0[1]
Analog Column Mux Input
5
O
TX_SHUT
DOWN
Output to disable PLC transmit
circuitry in receive mode
Logic ‘0’ - When the Modem is trans-
mitting
Logic ‘1’ - When the Modem is not
transmitting
6
I/O
P2[5]
7
I/O
I
P2[3]
Direct switched capacitor block input
8
I/O
I
P2[1]
Direct switched capacitor block input
9
Reserved
RSVD
Reserved
10
I/O
P1[7]
I2C Serial Clock (SCL)
11
I/O
P1[5]
I2C Serial Data (SDA)
12
I/O
P1[3]
XTAL_STABILITY. Connect a 0.1 F
capacitor between the pin and Vss.
13
I/O
P1[1]
I2C SCL
14
Power
Vss
Ground connection.
15
I/O
P1[0]
I2C SDA
16
I/O
P1[2]
17
I/O
P1[4]
Optional External Clock Input
(EXTCLK)[2]
18
I/O
P1[6]
19
Input
XRES
Active high external reset with
internal pull down
20
O
RXCOMP_
OUT
Analog Output to external Low Pass
Filter Circuitry
21
I
RXCOMP_
IN
Analog Input from the external Low
Pass Filter Circuitry
22
Analog Ground
AGND
Analog Ground. Connect a 1.0 F
capacitor between the pin and Vss.
23
I/O
P2[6]
External Voltage Reference (VREF)
24
Reserved
RSVD
Reserved
25
I/O
P0[2]
Analog column mux input and column
output
26
I/O
P0[4]
Analog column mux input and column
output
27
I
FSK_IN
Analog FSK Input
28
Power
Vdd
Supply Voltage
LEGEND: A = Analog, I = Input, O = Output, and RSVD = Reserved (should be left unconnected).
A,I , P0[7]
RSVD
FSK_OUT
A,I , P0[1]
TX_ SHUTDOWN
P2[5]
A,I ,P2[3]
A,I,P2[1]
RSVD
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
Vdd
FSK_IN
P0[4] , A, IO
P0[2],A,IO
RSVD
P2[6] , External VREF
AGND
RXCOMP_IN
RXCOMP_OUT
XRES
P1[6]
P1[4] , EXTCLK
P1[2]
P1[0] , XTALout,I2C SDA
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
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