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| 型號： | CY2212 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 124K |
| 代理商： | CY2212 |
CY2212
Document #: 38-07466 Rev. **
Page 8 of 10
Figure 12
shows the definition of LCLK cycle jitter and LCLK
10-cycle jitter. These parameters apply to the LCLK output,
and not to the Rambus channel clock outputs.
LCLK cycle jitter is the variation in the clock period, T, over a
continuous set of clock cycles. The difference between the
maximum period and the nominal period in the set of clock
cycles measured would be compared to the max spec listed in
the AC Device Characteristics Table on page 3. LCLK cycle
jitter is measured between rising edges at 50% of the output
voltage, and is measured continuously over 30,000 cycles.
LCLK 10-cycle jitter is the variation in the time of 10 clock
cycles, 10*T, where T is the clock period. The difference
between the maximum 10-cycle period and the nominal 10-
cycle period in the set of clock cycles measured would be
compared to the max spec listed in the AC Device Character-
istics Table on page 5. Note that the specification for LCLK 10-
cycle jitter is defined based on the measured value of LCLK
cycle jitter. LCLK 10-cycle jitter is measured between the first
rising edge and the tenth rising edge at 50% of the output
voltage, and is measured over 30,000 continuous cycles. t
JC,L
is defined as the LCLK output cycle jitter, and t
J10,L
is defined
as the LCLK output jitter over 10 cycles.
Measurement
The short-term jitter specification (over one to six cycles) for
the clock source is given as t
J
, as previously shown. Jitter
should be measured using a jitter measurement system that
has the flexibility of measuring cycle-to-cycle jitter as a
function of cycle count. It is important that the short-term jitter
be measured over consecutive cycles in order to prevent long-
term drift from causing overly-pessimistic results. When
measured over 10,000 consecutive cycles, the short-term jitter
measurements generate large amounts of data which can be
viewed in a histogram.
Figure 13
shows an example histogram
of data from a 4-cycle short-term jitter measurement, with
results that are within spec lines for t
J
. Note that the jitter is
specified as peak-to-peak, so the center of the histogram need
not be exactly zero.
Further details of jitter measurement methodologies are given
in the Rambus
DRCG-Lite Specification
Appendix A published
by Rambus, Inc.
t
4CYCLE,i
t
J
= t
4CYCLE,i
–
t
4CYCLE,i+1 over 10000 consecutive cycles
t
4CYCLE,i+1
CLK
CLKB
Figure 10. Short-term Jitter
t
PW+,i
t
DC,ERR
= t
PW+,i
–
t
PW+,i+1
CLK
CLKB
t
PW+,i+1
t
CYCLE,i+1
t
CYCLE,i+1
Cycle i
Cycle i+1
Figure 11. Cycle-to-cycle Duty Cycle Error
LCLK
T
10*T
Figure 12. LCLK Jitter
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