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參數(shù)資料
| 型號： | CY2212 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 124K |
| 代理商： | CY2212 |
CY2212
Document #: 38-07466 Rev. **
Page 7 of 10
Figure 9
shows the definition of cycle-to-cycle jitter with
respect to the falling edge of the CLK signal. Cycle-to-cycle
jitter is the difference between cycle times of adjacent cycles.
Equal requirements apply for rising edges of the CLK signal.
t
J
is defined as the clock output cycle-to-cycle jitter.
Figure 10
shows the definition of four-cycle short-term jitter.
Short-term jitter is defined with respect to the falling edge of
the CLK. Four-cycle short-term jitter is the difference between
the cumulative cycle times of adjacent four cycles. Equal
requirements apply for rising edges of the CLK signal. Equal
requirements also apply for two-cycle short-term jitter and
three-cycle short-term jitter, and for five-cycle short-term jitter
and six-cycle short-term jitter. t
J
is defined as the clock output
short-term jitter over 2, 3, 4, 5, or 6 cycles.
The purpose of this definition of short-term jitter is to define
errors in the measured time (for example, t
4CYCLE,i
) vs. the
expected time. The purpose for measuring the adjacent time
t
4CYCLE, i+1
is only to help determine the expected time for
t
4CYCLE, i
. Alternate methods of determining t
J
are possible,
including comparing the measured time to an expected time
based on a local cycle time, t
CYCLE,LOCAL
. This local cycle time
could be determined by taking the rolling average of a group
of cycles (5
–
10 cycles) proceeding the measured cycles.
However, it is important to differentiate this rolling average
from the average cycle time, t
CYCLE,AVG
, which is the average
cycle time over the 10,000 cycles. Using a long-term average
instead of a rolling average would define t
J
as a long-term jitter
instead of a short-term jitter, and would normally giver overly
pessimistic results.
Figure 11
shows the definition of cycle-to-cycle duty cycle
error. Cycle-to-cycle duty cycle error is defined as the
difference between high-times of adjacent cycles. Equal
requirements apply to the low-times. t
DC
,
ERR
is defined as the
clock output cycle-to-cycle duty cycle error.
t
PW+
t
CYCLE
CLK
CLKB
DC = t
PW +
/t
CYCLE
Figure 7. Duty Cycle
t
CYCLE
t
JL
= t
CYCLE,max
–
t
CYCLE,min over 10000 cycles
CLK
CLKB
Figure 8. Long-term Jitter
t
CYCLE,i
t
J
= t
CYLCE,i
–
t
CYCLE,i + 1 over 10000 consecutive cycles
CLK
CLKB
t
CYCLE,i+1
Figure 9. Cycle-to-cycle Jitter
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| CY2212ZC-2 | 制造商:Cypress Semiconductor 功能描述: |
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