- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366973 > CY2212 Clocks and Buffers PDF資料下載
參數(shù)資料
| 型號(hào)： | CY2212 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大?。?/td> | 124K |
| 代理商： | CY2212 |
CY2212
Document #: 38-07466 Rev. **
Page 5 of 10
The clock driver is specified as a black-box at the packaged
pins. The output characteristics are measured after the series
resistance, R
S
. The outputs are terminated differentially, with
no applied termination voltage.
Figure 3
below shows the clock driver implemented as a push-
pull driver. When stimulating the output driver, the trans-
mission lines shown in
Figure 3
can be replaced by a direct
connection to the termination resistors, R
T
. The values for the
external components are given in
Table 1
.
As mentioned previously, the clock driver
’
s output impedance
matches the channel impedance. To accomplish this, each of
the output driver devices are sized to have an R
OUT
of about
20 ohms when fully turned on. R
OUT
is the dynamic output
resistance, and is defined in the DC Device Characteristics
Table on page 3 of this data sheet. Since R
OUT
is in series with
R
S
, and that combination is in parallel with R
P
, the effective
output impedance is given by:
R
P
(R
S
+ R
OUT
)/(R
P
+ R
S
+ R
OUT
).
This calculation results in a effective output impedance of
about 27 ohms for the values listed in
Table 1
. Since the total
impedance is dominated by the external resistors, a large
possible range of R
OUT
is allowed. When the output is transi-
tioning, the impedance of the CMOS devices increases
dramatically. The purpose of R
P
is to limit the maximum output
impedance during output transitions.
In order to control signal attenuation and EMI, clock signal
rise/fall times must be tightly controlled. Therefore, external
filter capacitors C
F
are used to control the output slew rate. In
addition, the capacitor C
MID
is used to provide AC ground at
the mid-point of the R
P
resistors.
Table 1
gives the nominal values of the external components
and their maximum acceptable tolerance, assuming
ZCH = 28 ohms.
Table 1. Output External Component Values
Parameter
R
S
R
P
C
F
C
MID
Description
Value
68
39
15
0.01
Tolerance
±5%
±5%
±10%
±20%
Unit
ohm
ohm
pF
μ
F
Series Resistor
Parallel Resistor
Edge-rate Filter Capacitor
AC Ground Capacitor
R
S
C
F
R
S
R
P
R
P
Z
CH
Z
CH
R
T
=Z
CH
R
T
=Z
CH
Measurement Point
Measurement Point
DRCG Lite
C
F
C
MID
C
MID
Figure 3. Output Driver
R
S
C
F
R
S
R
P
R
P
Z
CH
Z
CH
R
T
= Z
CH
R
T
= Z
CH
Measurement Point
DRCG Lite
C
F
C
MID
C
MID
Z
CH
Z
CH
R
T
= Z
CH
R
T
= Z
CH
Measurement Point
C
MID
R
X
R
X
R
X
R
X
Figure 4. Output Driving Two Channels
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY22313 | Clocks and Buffers |
| CY2250SC-1 | CPU System Clock Generator |
| CY2254 | CPU System Clock Generator |
| CY2255 | CPU System Clock Generator |
| CY2256PVC-1 | CPU System Clock Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2212ZC-2 | 制造商:Cypress Semiconductor 功能描述: |
| CY2212ZC-2T | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| CY2212ZXC-2 | 功能描述:鎖相環(huán) - PLL Rambus Lite Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY2212ZXC-2T | 功能描述:鎖相環(huán) - PLL HI Freq PECL Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY2213 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High-Frequency Programmable PECL Clock Generator |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。